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CDC72010EVM

Wenjun Huang
Expert 1770 points
Other Parts Discussed in Thread: CDCE72010

I am now trying to use the CDCE72010EVM in order to use the CDCE72010 in my hardware design.

I have problem using the CDCE72010EVM.

1. From the schematic of CDCE72010EVM, it seems that the 4 external loop filters are configured for 491.52MHz VCO output frequency and 10MHz input frequency. Is that so? Could I change the VCO output frequency to some other value other than 491.25MHz or is it determined by the external loop filters?

2. I am not inputting any clock into PRI and SEC, yet I am getting some output from clock output 0. Is it due to VCXO output? What is the correct way to use the EVM? Must I input a clock reference in PRI or SEC and use VCXO to synchronize the output clock to the clock reference.

3. Could someone provide a ini file for me to understand how the EVM works. Eg. provide clock output like 100MHz, 66MHz and 312.5MHz using some input clock frequency.

Thanks.

  • 0
    TI__Mastermind 30825 points

    Wenjun,

    This doesn't appear to have any relation to C66x Multicore DSPs.  I'm moving this to the Clocks and Timing section of the forum.  Please make sure you post in the correct area of the forum to ensure prompt responses.

    Best Regards,
    Chad

  • 0 in reply to Chad Courtney
    TI__Guru* 81034 points

    Hi Wenjun,

    I have attached an examply ini file and I recommend also downloading the EVM User Guide from ti.com. There are switches for 4 different loop filters on the board, and the loop filter values can be changed to optimize the loop bandwidth for your application. If no input is connected, the output will still run because of the VCXO on the board, but the PLL will not be locked.

    This ini file generates frequencies divided from the 491.52MHz VCXO on the EVM and a 10MHz LVCMOS input needs to be provided to PRI_REFP.

     

    Best regards,

    Matt

    http://e2e.ti.com/cfs-file.ashx/__key/communityserver-discussions-components-files/48/0027.CDCE72010_5F00_Default_5F00_Config_5F00_2p1.ini

  • 0 in reply to Matt Sunna
    Expert 1770 points

    Hi Matt,

    Thanks for the prompt reply. 

    May I know why is the VCXO 491.52MHz? Isn't a VCXO a device that output frequency depending on voltage level, so it should be a variable frequency device? Can I use a different frequency (like 20MHz) for the reference clock (PRI or SEC)? Can I operate the VCXO to be other voltage other than 491.52MHz like 200MHz?

    Is the loop filter values just to adjust the loop BW? How to optimize the loop BW? What is meant by optimizing the loop BW?

    Am I right to say that the VCXO is the real clock input and the PRI and SEC are reference clock to synchronize the VCXO clock input to ensure that the output are synchronize to the reference clock?

    On the schematic, for pll loop filter 1, there is 1kHz, PFD=5MHz, CP=3mA. What does the 1kHz mean? Why is the Charge Pump current 3mA? Why is the phase frequency detector 5MHz?

  • 0 in reply to Wenjun Huang
    TI__Guru* 81034 points

    Hi Wenjun,

    VCXO typically have very tight tuning ranges, so it is important to buy a VCXO for the specific frequency desired. The CDCE72010 will tune the VCXO in order to lock to the input clock. The 491.52MHz VCXO is a very common frequency for clocking ADCs in wireless communications systems. This can be changed to 200MHz as mentioned by replacing the VCXO. The loop bandwidth sets the characteristics of the low-pass filter applied to the VCXO tuning voltage. A narrow loop bandwidth is helpful when the input reference clock needs to be cleaned as the output phase noise will be dominated by the VCXO. For a wide loop bandwidth, the output phase noise will be similar to that of the input, so this is okay when the input reference is a very clean clock. 

    The attached GUI (not yet released to the web) has a new loop filter tool that helps to select components and simulate the loop filter.

    Best regards,

    Matt

    4617.CDCE72010_Setup.zip