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CLOCKING SOLUTION

eli
Guru 13485 points

Other Parts Discussed in Thread: LMK00105

I have a 125Mhz low jitter oscillator working at 3.3V and I have to provide it to a Phy.

However, this Phy works at 2.5V and requires a 700pS rise/ fall time and at least 20/ 80% duty cycle.

This requires, I think, a clock distributer/ clock buffer, to come between the oscillator and the Phy.

Do you have such a clock distributer (minimal output pins will do as I need only one clock) ?

Off course I need in in industrial temperature span...

  • 0
    TI__Intellectual 915 points

    You may consider the LMK00105, http://www.ti.com/product/lmk00105.  This is a 5 output LVCMOS buffer which has adjustable output voltage levels.  This buffer should also meet your rise/fall times and temperature range requirements. 

    Hope this helps.

    Jon

  • 0 in reply to Jonathan Kolbrak
    Guru 13485 points

    The LMK00105 datasheet speaks of a 2V/nS as a mandatory requirement for differential input.

    We use single ended input from a very close by 3.3V CMOS output oscillator.

    What is the required rise time (slew rate) of this oscillator to cooperate properly with the LMK?

    Which option of single ended connectivity will you recommend for such scenario?

     

  • 0 in reply to eli
    Guru 13485 points

    I tried to see if I could find your note about the 2.5V limitation in the datasheet, but I didn't.

    This brought me the idea that I don't know, and I didn't see it either in the datasheet, to

    which Bank (A or B) is each of the "control" pins related to.

    If I want to pull up the SEL pin for example, to which voltage I should connect it ? BankA (3.3V) or BankB (2.5V) ?

    Is there a list in the datasheet of which Bank each pin belongs to?

    Can you provide me with such a list?

  • 0 in reply to eli
    TI__Mastermind 32575 points

    See the Pin Descriptions table for the Vddo supply pins associated for each output bank. 

    The SELx and OE input control pins can be pulled up to Vdd (core supply) or Vddo (output supply), as long as you meet the VIH min level (1.3V/1.6V @ Vdd=2.5V/3.3V). 

    Regards,

    Alan

  • 0 in reply to eli
    TI__Mastermind 32575 points

    Not meeting the input slew rate will cause the output noise floor / additive jitter to degrade according to the typical plots shown in the datasheet. The device should still be functional at lower input slew rates, but faster slew rate ensures the additive noise/jitter of the device will not be degraded. Of course, you also need to consider how much RMS jitter your input clock will have as this will add in root sum squared fashion with the additive RMS jitter of the buffer device. 

    See page 9 in the datasheet (section 14.1) for interfacing a single ended clock to the clock inputs of the device.

    Regards,

    Alan