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CDCE62005 and duty cycle issue when using dividers

Marcin Ostopinko
Prodigy 20 points
Other Parts Discussed in Thread: CDCE62005

Hello,

our question is related with output duty cycle in CDCE62005 when using Smart MUX and output divider set to 1.

When we route input LVCMOS clock from reference input though Smart MUX(with the reference divider set to eg. 2) to one of outputs which has divider value set to 1 (bits 20:13 in regs 0-4 = 0xA0) we can see on the oscilloscope that the signal has an duty cycle of 80/100. Configuration example:

inputClock on ref 1 -> Smart MUX with divider set to 2 -> output divider 1 set to 1 -> output clock with duty cycle 80/100

When we set the output dividers to values other than 1 the duty cycle of the output clock is 50/100 <- this is what we want. Configuration example:

inputClock on ref 1 -> Smart MUX with divider set to 2 -> output divider 1 set to 2 -> output clock with duty cycle 50/100

The frequency value in both cases is correct.

How can we get 50/100 clock duty cycle with output divider set to 1 when routing the clock though Smart MUX with div=2? The input clock is an LVCMOS clock with the duty cycle of 50/100. When we route the reference input directly to output(without using smart Mux) we always get the 50/100 duty cycle.

Can somebody try to reproduce this on the EVM? Is this a known issue with a fix? We dont want to use the PLL.

Best regards,

Marcin

  • 0
    TI__Expert 4150 points

    Hi Marcin,

    yes, this is a known phenomena. I don't think there is a work-around, unless you would leave the pre-divider at one, then post-divide by 2 on your output buffer, and either run your PFD frequency higher or divide by two after the smartmux. This may however not be possible based on your other input. All the best. Sincerely,

    Falk Alicke

  • 0 in reply to Fritz
    Prodigy 20 points

    Hello,

    thank you for the answer. I have an additonal question regarding how to protect the inputs and outputs of the CDCE62005 chip.

    I want to drive other devices with the output clock over a coaxial cable. Is a 10R resistor a sufficent protection against reflections? I dont know if the device at the other end of cable will have a termination.

    Can you also advise how to protect inputs against single ended signals having too high voltages or below GND . I want to connect the input CMOS clock also over an coaxial cable. The termination should be included in the design.

    Best regards,

    Marcin