How to avoid noise in Clock Generation CD4047BM.??

Harish Kumar1

Hi,

I am using CD4047BM for generating free running clock for my FPGA. Below is the part of circuit.

If I place CRO probe at the output wrt Gnd, I found lot of noise (approx 2V noise). Can you please suggest, how to avoid the noises in my circuit..?

Regards

Harish

over 12 years ago

0 Avi Chami1 over 12 years ago

Mastermind 7395 points

What is your Vcc?

R is too large, try use a smaller value, like 500K, and a larger capacitor. If you still have problems, you can try smaller values and then divide the frequency inside the FPGA

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How to avoid noise in Clock Generation CD4047BM.??