Other Parts Discussed in Thread: CDCE62005, CDCM6208, LMK04906
Hello to all,
for a new project i'm evaluating the CDCE62005 working in clock cleaner mode with programmable output skew.
I've read the latest documentation for this component (also the technical notes for the newest CDCM6208 and some answers on this forum) and it seems
there is an unavoidable uncertainty of one VCO prescaler output clock period when outputs are syncronized using SYNC_N input.
Try to explain the problem: assuming SYNC_N low-to-high transition applied with some setup margin respect to Reference Clock (freq = 40MHz, tsu = 10ns for
example), the first D-flip-flop of synchronization chain will never go into metastability, but what about the 2nd D-flip-flop driving the output divider ?
According to output 'synchronization circuitry block diagram' and 'Output Synchronization Diagram' on page 55 of datasheet,
when SYNC_N signal has been captured by internal Reference-Clock on first stage, will the 2nd register respond on the first PreScalar-Clock edge
following the Reference-Clock edge in a predictible way (i.e. assuming a VCO prescaler frequency of 1GHz typ) ?
For the new component CDCM6208 there is an explicit note about output synchronization:
"...The SYNC feature is particularly helpful in systems with multiple CDCM6208. If SYNC is released simultaneously
for all devices, the total remaining output skew uncertainty is ±1 clock cycles for all devices configured to
identical pre-scaler settings. For devices with varying pre-scaler settings, the total part-to-part skew uncertainty
due to sync remains ±2 clock cycles."
Does this apply also for the CDCE62005 ? Is there a VCO-prescaler minimum frequency value that guarantees this tight timing ?
(I wish to use the CDCE62005 as programmable delay line for a 40MHz clock signal playing with different Output Coarse Phase Adjust Settings).
Thank you for your attention, Best Regards
Stefano
