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CDCE62005 has no clock out!

Other Parts Discussed in Thread: CDCE62005

Hi,everyone .

          I use cdce62005 to supply clock to 6678 . the power supply to cdce62005 is right,the Auxin clock input is a 25MHz crystal and the 25MHz crystal is good.In my opinion ,before we configure the cdce62005, output 0 will be 156.25Mhz,but there is no frequency out,why?

and If we want to configure the cdce62005,How many registers should be written by SPI port, 8 or 9? Should we configure reg0008,or just ignore it?thanks

  • Hi Quoping,

    if you followed the timing requirements at Power-Up, the correct default EEPROM setting will be loaded into the RAM and the device will provid the expected output frequency. You may like to check for example that the SPI_LE is high before that the PowerDownN pin goes to high. This will ensure that the value on the EEPROM will be loaded correctly on the RAM. We usually suggest customer to apply a big (>100pF) cap on the PowerDownN pin, this will make this pin to reach the High value after the SPI_LE pin during power up.

    You may need to write the register 8 as well, taking care of the reserved bit and considering that other bits are Read-Only, therefore no specific need to configure them.

    Let me know if you need additional support

    Leandro

  • Hi leandro

    thank you for the reply. do you konw where can I find the electrical characteristics operating condition for Aux input?  in my project, the amplitude of 25MHz crystal for Aux input is only 1V.

  • Hi Guoping,

    as long as the XTAL parameters are in the range of the what it is specified in the CDCE62005 datasheet you do not need to worry about the signal amplitude on the AUX_IN. As you may know, the XTAL itself can't oscillate. It needs an oscillator circuit which "substains" the oscillator and which is inside the CDCE62005. The oscillator circuit defines the oscillation amplitude at AUX_IN.

    I hope this helps you.

    Best regards,

    Leandro

  • Hi leandro.

    now the aux input is 25MHz. We make the SPI_LE high,and power_down low after power up.then  We make power_down high.and there is no output. where did we miss?

  • Hi Guoping,

    could you please confirm that the sequence at power up? It should be: VDD rises up, SPI_LE follows VDD with a small delay (100ns) and later PDn is released. In case of slow supply ramp you may need to place a small (20pF) cap on SPI_LE pin and a bigger (>100pF) cap on PDn pin.

    Would it be possible for you to try this out?

    Thanks and best regards,

    Leandro

  • Hi Guoping,

    I have another suggestion for you. Would you please try to write in the Register 8 bit7 a 1 after power up to be sure the device is not in Sleep Mode?

    Thanks and best regards,

    Leandro

  • Hi Leandro_z

    thanks for your reply,now We can configure the cdce62005 and there is clock out . the input is 25MHz crystal to aux input, we want to have 100MHz LVDS in output 0 and output 2, 66.7MHz LVDS in output 4. but there is something wrong.the common-mode voltage of the output frequency is not 1.2V.it's about 1.3V,why?

    my register setting is

    reg0    = 32'he9840320;             
    reg1    = 32'h81840301;             
    reg2    = 32'he9840302;             
    reg3    = 32'heb860303;             
    reg4    = 32'he9020314;             
    reg5    = 32'h10100b25;             
    reg6    = 32'h84be0786; 

    reg7    = 32'hbd00_37f7;          

        thank you!

               

  • Hi Guoping,

    we specified in the d/s 1.24V as typcial value of the common mode voltage for LVDS output. This voltage dependes on the supply voltage and the termination scheme you applied at the output. Are you sure that you are using exactly 3.3V or is it perhaps a bit higher? What is your termination scheme?

    if you are using the 50Ohm internal termination of the scope, please ensure that both YxP and YxN to the scope.

    Best regards,

    Leandro