We have an issue with the CDCE62005. The problem is that we somtimes havent a pll lock after a power on cycle and because of this the output frequencies were not stable. Our system consists of a C6672 DSP the CDCE62005 Clock generator which generates 100 MH, 200MHz, 250 MHZ, 100MHz and 100MHZ on its clock outs and a PIC microcontroller which makes the power sequencing for the DSP. We use a 25MHZ Crystal at the AUX Input.
The Register settings inside the CDCE62005 are:
0xeb060300, // 0
0xeb860301, // 1
0xeb840302, // 2
0xeb060303, // 3
0xeb060314, // 4
0x00000b25, // 5
0x120e03e6, // 6
0xfdc1f9e7, // 7
0x80009c98 }; // 8
We tried everything which we found in this forum, e.g adding the >100pF to the PowerDownN pin, adding a external loopback filter but nothing helps.
Any ideas what can help ?
