Lock Problems & CDCD62005 - Related to "Reg_Cap1" pin

Richard,

I've taken a look at your settings, and loaded them into one of our EVMs to give it a test. The device seemed to be locking OK.

Regarding the general stability of the lock, we do have a few suggestions that might help. For increased stability of your system, and better jitter performance, you should try changing the PFD frequency to be 25MHz, rather than 12.5MHz. I would also suggest that there are some improvements that can be made to your loop filter. I attached the new INI settings for you. Go ahead and load this into the GUI, or open it in notepad to see the changes/register settings. Note that I also decreased the charge pump current from 2.5mA to 1mA for helping with stability.

http://e2e.ti.com/cfs-file.ashx/__key/communityserver-discussions-components-files/48/5342.OptimisedPerformanceAndStablilty.ini

I hope this helps to solve your issue. Let me know if your problem persists. Thanks!

Regards,

Brandon Vonk

Hi Brandon,

Thanks for the updated register values.  Unfortunately, this doesn't fix my problem board.

I'm not sure if I mentioned in my original post that I have four boards, three of which lock okay and this one problem board that does not lock reliably.  I have tried the new register values on the 'good' boards and they still lock reliably.

We have checked the solder connections and they look fine, as does the source clock.

Any ideas?  Is the sensitivity of the "Reg_Cap1" pin a clue?

Cheers,

Richard

PS: I should have mentioned that I am changing the register values slightly, by setting the LOCKDET bit high, so that we only get a lock after 64 PFD cycles.

Hi Brandon,

We've been doing further investigations.  When the capacitor attached to "Reg_Cap1" is removed, our device locks reliably.  Can you let me know what this pin is for?

I was wondering if it is noise from my ground plane being coupled into the device via the "Reg_Cap1" pin.  However, we have another CDC62005 on the same board which is wired to an output of the problem CDC62005.  If the problem device locks, the second always locks without trouble.  Both devices have very similar layouts.  Both attached to the same GND planes.

Any ideas?

Cheers,

Richard

Hi Richard,

This capacitor is used by an internal voltage regulator. You might be right that noise is being coupled into the device through this cap somehow. May I ask what inspired the idea to remove this capacitor? Is it close to another noisy signal that could inject noise?

Best regards,

Matt

Hi Matt,

The capacitor is very close to the "Reg1_Cap" pin, on the same side of the board as the device.  The trace from the cap to the pin is very short and the other end vias directly to a ground plane.  There aren't any noisy signals near this cap.

The reason we removed the cap was because my colleague noticed that if he stuck his finger on the cap that the device locked more reliably. We then found that removing the cap meant it would lock every time.  [ I think with Brandon's changes to register settings that this cap isn't so sensitive to a finger being placed on it, but removing it still makes locking more reliable].

Cheers,

Richard

Edit: Section in square brackets found to be untrue.

Hello Richard,

it seems like this thread was overlooked for unknown reasons. Let me follow up on this.

As i understand you have 4 prototype boards. Each of those boards have 2 CDCE62005 onboard. The register setting is the same for all of the CDCE62005 (?!). At one prototype one CDCE62005 does not lock reliable. If the Reg1_Cap is removed the device looks always. Is this summary correct?

What is the input clock source of the failing CDCE62005?

Did you had a chance to replace the failing part on the PCB? Any effects?

-> If not, could you please send the schematics and layout files which relate to the CDCE62005?

Best regards,

Julian

Hi Julian,

I now have 9 prototype boards.  8 have a problem with the first CDCE62005 locking.  1 does not have a problem.  The 8 problem cards suffer to varying degrees i.e. some fail to lock more often than others.

Each board has two CDCE62005 devices.  The first device has the problem locking and is trying to lock to an LVDS oscillator.  See enclosed schematic.

The register settings for the two devices is different.  I program both from an FPGA.  My values are:

Device1:

rom(0) := x"eb400020";
rom(1) := x"eb400001";
rom(2) := x"eb400002";
rom(3) := x"eb020303";
rom(4) := x"eb020314";
rom(5) := (x"100c0c75" or x"40000000");                   -- lockdet only after 64 cycles
rom(6) := x"208e0106";
rom(7) := x"bd933df7";
rom(8) := ((x"208e0106" or x"80000000") and x"fbffffff"); -- ensure ms bit is set to enable man calibration mode
                                                          -- clear ENCAL bit
rom(9) := (x"208e0106" or x"84000000");                   -- ensure ms bit is set to enable man calibration mode

Device2:

rom(0) := x"eb800320";
rom(1) := x"eb800301";
rom(2) := x"eb800302";
rom(3) := x"69800303";
rom(4) := x"eb800314";
rom(5) := (x"103c0875" or x"40000000");                   -- lockdet only after 64 cycles
rom(6) := x"04be09a6";
rom(7) := x"bd92bde7";
rom(8) := ((x"04be09a6" or x"80000000") and x"fbffffff"); -- ensure ms bit is set to enable man calibration mode
                                                          -- clear ENCAL bit
rom(9) := (x"04be09a6" or x"84000000");                   -- ensure ms bit is set to enable man calibration mode

The registers are written in the order shown above.  Registers to device 2 are only written once device one locks.

The register values were suggested by your colleague.  I don't think the version of the CDCE62005 EVM software they used has been released yet.

On a few sample boards, if the Reg1_Cap is removed the device always locks.

I'll try and upload layout files later.

Cheers,

Richard

Don't think the schematics worked on the last post - adding them as a file doesn't seem to work.

Here's the layout...

Hello Richard,

the schematics and the layout is fine. Could you please try in the first device to disable the input termination? This can be done be setting bit 8 register 5 to '1'.

Best regards,

Julian

Hi Julian,

Well spotted, input termination should have been disabled.  Unfortunately this does not fix our problem.  I enclose a copy of the modified code so that you can confirm I've changed it correctly.

rom(5) := (x"100c0c75" or x"40001000"); -- lockdet only after 64 cycles
                                        -- internal i/p termination disabled

Are you able to check the loop filter settings.  I only have a beta version  1.4.6 of the GUI software which doesn't work very well.

Cheers,

Richard

Hello Richard,

your loopfilter had a PM of 55deg. so, it should be ok.

This loopfilter setting gives you a bit more margin: PM=63.6deg

Register 7: 0xbd91fdd7

Register 6: 0x307e0106

Please make sure, that REF_SEL is at "high" level and all VDD are in the specified voltage range.

If this does not work, Please post a screenshot of the input signal and the output signal (Y0).

Best regards,

Julian

Hi Julian,

Sorry for the delay.  I've been experimenting...

Can you please confirm if a delay is required between my SPI writes that configure the device registers and a write that kicks off a manual calibration.  [Note: I am never writing my settings to the EPROM. So when released from Power Down the device will load in the default register values, which get overwritten by my SPI writes].

If you look at my register values above, I was writing values rom(0) through to rom(9) one after another i.e. no delay before kicking off manual calibration with my last write.

The datasheet does not talk about a delay in the sections that describe manual calibration.  But the section on "Startup Time Estimation" talks about t_delay before the calibration time.  I must admit I assumed this was all handled in the device and this section was telling how long to wait before expecting a lock.

Cheers,

Richard

Hello Richard,

it is not necessary to do a wait before the calibration routine. we do a similar write routine during production test at 20MHz SPI clk frequency. Anyway, you need to ensure, that the XO has a stable output if you start the calibration.

Do you write to the 2 devices sequentially?

Best regards,

Julian