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cdce62005 lock problem

Ping Yeung
Prodigy 80 points

Hi, we are doing a design based on the C6678 EVM kit, which has two CDCE62005 chips cascaded.  The first chip runs from a 25MHz crystal and outputs (among other frequencies) a 100MHz output that is routed to the input of the second chip. The second runs from this 100MHz input.  The register setup for both chip is done by an FPGA with delay between them to allow the input clock for the second chip stablize.

However, we are having trouble getting the second chip to give a PLL lock.  The first chip ALWAYS locks while the second chip NEVER locks. 

The register setting sequence for the second chip is as follows:

x"E9840320", x"69840301", x"E9800302", x"E9840303", x"69860314", x"101C0A65", x"04BE0F06", x"FD0037F7", x"80BE0F06", x"84BE0F06", x"80008CD8", x"80009CD8"

Any help to solve this problem will be greatly appreciated. Thank you.

  • 0
    TI__Guru* 81035 points

    Hi Ping,

    It looks like these register settings are designed for a 25MHz input, so this needs to be modified to work with 100MHz. I modified the file and the new settings can be viewed below. Let me know if this fixes the problem you are seeing.

    http://e2e.ti.com/cfs-file.ashx/__key/communityserver-discussions-components-files/48/7418.New_5F00_Settings.ini

    Best regards,

    Matt

  • 0 in reply to Matt Sunna
    Prodigy 80 points

    Matt,

    Thanks for the quick response. With the new setting, I am able to get the VCO to lock. However, I got 200MHz at Channel two output instead of 312MHz. Is xE9800302 the correct setting for 312MHz at channel 2? Thank you very much.

    Ben

     

  • 0 in reply to Ping Yeung
    TI__Guru* 81035 points

    Hi Ben,

    These settings will not provide a 312MHz output. Can you send me the desired frequency at each output and I can create a new configuration file? How were the original settings generated as these also would not generate the 312MHz output?

    Best regards,

    Matt

  • 0 in reply to Matt Sunna
    Prodigy 80 points

    Matt,

    I have a 100 MHz input clock at PRI_REF. I need to get 100MHz output at channel 0 and channel 3, 312MHz output at channel 1 and 2. Thank you very much.

    Ben  

  • 0 in reply to Ping Yeung
    TI__Guru* 81035 points

    Hi Ben,

    Here are the new settings. Note that the PLL is bypassed on channels 0 and 3 since 100MHz cannot be generated from the same VCO frequency as 312.5MHz.

    http://e2e.ti.com/cfs-file.ashx/__key/communityserver-discussions-components-files/48/6215.New_5F00_Settings.ini

    Best regards,

    Matt

  • 0 in reply to Matt Sunna
    Prodigy 80 points

    Matt,

    I tried the setting you suggested in the new ini without success. Four things I noticed with this new ini.

    1. The VCO failed to lock

    2. Is it true that the setting for register 0x00 (0xEB400020) and 0x03 (0xEB400003) to be the same except bit 3 to 0?

    3. I expect the setting to register 0x01 (0xEB800321) and 0x02 (0xEB800302) to be the same except bit 3 to 0?

    4. For a bypassed clock, is it ok to have LVPECL input and LVDS output? I can not observe any clock output from the bypassed 100MHz outputs.

    Ben

  • 0 in reply to Ping Yeung
    Prodigy 80 points

    Matt,

    Dont worry about it. I got it figured out. I have to modify the register 0x05 to 0x103C0A75 to accomodate my input clock.

    Thank you for all your help.

    Ben