Other Parts Discussed in Thread: LMH1983
I have a pcb with an LMH1983, normally used for generating a pixel clock genlocked to a video signal.
There is the need to have it genlock to another type of signal, so the idea is to have it free-running, and implement a very low bandwidth control loop by periodically adjusting the values of registers 0x18 and 0x19, which have the VC_Free MSB and LSB values, which corresponds to the voltage sent to the VCO when the LMH1983 is free running. This adjustment can be slow, and the main purpose is to avoid overrunning or underrunning an internal frame buffer, so basically keep the top-of-frame somewhere in the middle.
However, the signal needs to be relatively stable (this is for hdsdi), and I am afraid that since the MSB of the VC_Free is on a separate register than the LSB, that extreme intermediate values would occur from the moment one register is updated (say the MSB part of VC_Free), to when the other one is, since they cannot be updated simultaneously. For example, when going from 1000000000 to 0111111111, extreme intermediate values could be 0100000000 or 1011111111, depending on which register is written first. I imagine this could cause a jump in the VCO frequency (subject to its filters), and cause problems with the sdi receiver (hdsdi receivers are relatively touchy and lose lock easily, making the video signal glitch).
Is this the case (frequency jumps due to extreme intermediate values in the VC_Free registers when updating them), and if it is, is there any way around it?
Thank you.
