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Ultra low skew clock distribution

Xiang Chao
Intellectual 360 points
Other Parts Discussed in Thread: LMK04100, LMK00301

Hello,

 

I need an ultra low skew clock distribution scheme :

 

1 to 36 @300MHz

clock skew between any 2 clock paths : < 20 ps

 

I checked some parts form TI, and found that the propagation delay between varies too much from path to path.

Could somebody give me a suggestion?

 

Thanks

 

Chao Xiang

  • 0
    TI__Mastermind 28011 points

    Chao,

    For propogation delay of <20 ps, we do not have anything to my knowledge, but if the key spec is clock skew between any 2 clock paths, perhaps channel to channel skew is OK if you are just using 1 device to generate all clocks.

    As for a skew from channel to channel, we do have some devices that might work.

    The LMK04100 family typically has skew on the order of +/- 4 ps.  As for a maximum spec, this is an issue for testing in production so we tend to shy away from this.

    The LMK04800 is a similar story where we say typically the maximum is 30 ps.  This means it is closer to 4, but because we have issues testing in production, we shy away from a guarantee.  The cable alone can easily cause 30 ps of error and not tightening the cable can easily make 10 ps difference.

    The LMK001 and LMK03 family of buffers is also a similar story.

    Regards,

    Dean

  • 0 in reply to Dean Banerjee
    Intellectual 360 points

    Hi Dean,

     

    I have a single ended -5dBm clock signal, and I need to fan it out to 9 ADC modules with as little skew as possible.

    What kind of clock buffer will work for me?

     

    Thanks

     

    Chao Xiang

  • 0 in reply to Xiang Chao
    TI__Mastermind 32575 points

    Hi Chao Xiang,

    Please consider the LMK00301 as a 10-output differential clock fanout buffer/level translator for driving multiple ADCs with low skew (< 50 ps max between all outputs) and low additive jitter.

    See this E2E post for more info on LMK0030x family of low-jitter devices. 
    http://e2e.ti.com/support/clocks/f/48/t/208057.aspx

    For best performance, consider using a low-noise amplifier to increase your input clock signal amplitude and also convert it to differential input signal to maximize the input slew rate.  It is recommended to have input slew rate above 3 V/ns.  Refer to the typical characteristic performance to see how additive phase noise/jitter performance is impacted by input slew rate.

    Regards,
    Alan