Hello all,
I'm having some problems trying to use a CDCE72010 chip in one of our designs. We are using a 25Mhz reference clock that can be input to the IC through primary or secondary input, and a 250Mhz VCXO. We are generating several differential output clock signals. The problem is that PLL_LOCK status bit (REG12.6) is always '0'. In fact, PRIACTIVITY and SECACTIVITY status bits (REG12.25-26) are always '1', even when primary clock is not present in the circuit. Here is the configuration we are using (see attached file):
[REGISTERS]
REG0=E80802F0
REG1=E9800051
REG2=21060002
REG3=E9800003
REG4=E9800104
REG5=68000005
REG6=68000006
REG7=68000027
REG8=68000178
REG9=69000C09
REG10=0024000A
REG11=0000004B
REG12=0000180C
Please, could anybody tell me if there is something wrong with this configuration or if the problem is outside the CDCE72010?
Best regards.
Sergio