Other Parts Discussed in Thread: CDCM7005
Hello Guys,
I have a customer who is working on CDCM7005 device to synchronize the clock for differnt subsytems.
He has some queries regarding the device functionality
CDCM7005 is used as Buffer / divider mode only.
Input Frequency = 500MHz (RF clock) & they have already converted to LVPECL level for CDCM7005 input.
For reset they have made provision of RC network.
After powering the device & Reset release what will be the output Frequency at all the output? They are expecting the output = 3.9MHz
Question is importnat as their host controller(FPGA) is also getting the clock from CDCM7005 output, so after getting the clock they FPGA will reconfigure the CDCM7005 to desire devider values to incerase the clcok of FPGA.
Or they need seperate host controller in this case?
Can somebody help here?
Thanks,
Mitesh
