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LMK0480x (Clock Distribution Mode, 2GHz)

Jonathan Eckert
Prodigy 10 points
Other Parts Discussed in Thread: LMK04906, LMK01801

Greetings,

I need to distribute high speed phase-matched clocks to multiple data converters.  Let's say the master is 2GHz SE sine wave (amplitude could be set 0-10dBm) and I need 4x 2GHz outputs, 4x 1GHz outputs and 4x outputs divided down even further, but TBD.     

I was wondering if I can do all that with a single LMK0480x part in "Clock Distribution" as shown in section 5.5/Figure 5 of the data sheet.  This configuration shows the use of CLKIN1/FIN/FBCLKin (pins 25/26) used as the input,  and clock dividers and delay functions.

However, the DS electrical characteristics say that Clkin fMAX is 500 MHz,  FBCLKin fMAX is 1000MHz, and Fin fMAX is 3100MHz.

I think this means I can use pins 25/26 up to 3GHz as Fin in the Clock Distribution mode but I can't tell.  The notes say AC-coupled MODE=3 or 11, but for Clock Distribution, the mode is listed as 16.

Also, the data sheet for LVDS/PVPECL clock outputs say CLKout fMAX is 1,536 MHz minimum, so from this, I can't tell if I am guaranteed operation up to 2+GHz.

Any idea how fast I can use the clock distribution if the PLLs aren't used?

 

 

 

  • 0
    TI__Mastermind 32575 points

    Hi Jonathan,

    Yes, LMK0480x and LMK04906 parts can support Clock Distribution Mode using CLKin1/FBCLKin/Fin port to distribute to clock outputs CLKout0-11.  This is a multi-use clock port that's internally routed depending on the device mode.  The max input frequency spec for "Fin" of 3.1 GHz applies for clock distribution as well as external VCO modes.  In Figure 6 of the datasheet, the detailed block diagram shows that the Fin path drives the Clock Distribution Path and CLKout channels via Mode Mux1. 

    See Note 13 below (from LMK04800 datasheet) regarding input slew rate requirements to achieve best phase noise performance, as this relates to your input sine wave amplitude setting.

    "Note 13: In order to meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all input clocks is 0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance will begin to degrade as the clock input slew rate is reduced. However, the device will function at slew rates down to the minimum listed. When compared to single-ended clocks, differential clocks (LVDS, LVPECL) will be less susceptible to degradation in phase noise performance at lower slew rates due to their common mode noise rejection. However, it is also recommended to use the highest possible slew rate for differential clocks to achieve optimal phase noise performance at the device outputs."

     Please also note the following caveats if you intend to operate some outputs (i.e. 4x 2 GHz) above the warranted max output frequency of 1.536 GHz for LVDS/LVPECL:

    1. Analog delay option may not operate at frequencies above the warranted max output frequency.
    2. Output swing specifications may not hold above the warranted max output frequency.  See datasheet section 14.0 for LVDS and LVPECL output swing vs. frequency characterisics.

    As an alternative to LMK04800/4906, you may also consider the LMK01801 divider-buffer.  It operates up to 3.1 GHz, has very low additive jitter, and has some pin controlled settings to configure the output dividers and output signaling formats.

    Regards,
    Alan