DIFFERENCE BETWEEN CDCM7005 & LMK4002

These two devices are not really suitable for direct comparison.

The CDCM7005 is single loop PLL and designed to operate with an external VCO/VCXO, so in many cases the performance of the device is mostly related to the performance of the VCXO/VCO chosen to be used with the CDCM7005.  So if you want an 800 MHz output, you must use an 800 MHz VCO.

The LMK04002 is dual loop PLL and designed to operate with an external VCXO.  This VCXO can be low frequency compared with output frequencies and the second PLL/internal VCO will achieve frequency multiplication.

  Futher, in both cases... the selected VCO/VCXOs used in jitter cleaning will impact final performance.

Here are some key questions:

  - In what integration bandwidth do you require jitter cleaning?  Example: 100 Hz to 40 MHz, 12 kHz to 20 MHz, 1 MHz to 100 MHz, etc.

  - What is the cleaned phase noise or jitter (/w bandwidth) target?

  - With CDCM7005 - what VCO/VCXO would you use?

  - With LMK04002 - what VCXO/crystal would you use?

Please note, the clock design tool can allow you to simulate LMK04002 performance.  For most accurate results you will need to load the phase noise profile of the VCXO you will use, and the reference noise will help you design the proper loop bandwidth for PLL1.  The download and several videos on how to use this tool can be found at:

http://www.ti.com/tool/clockdesigntool

73,

Timothy

Hi Timothy,

Nice to hear from you !

1. In your statement you have mentioned that to get 800MHz output in the CDCM7005 I need to use 800MHz VCO ?whether 800MHZ external VCO is cupulsory then what is the use of PLL ?

2. The VCXO planned for the CDCM7005 is 571AEC000107DG from silicon labs

3. Integration bandwidth: not yet decided

4. Target phase noise: minimum of 125dBc/Hz @ 1KHz offset

5. Kindly provide a link for the clock design tool of  CDCM7005

Regards,

Rajesh.S

Hello Rajesh,

1. In CDCM7005 the external VCO/VCXO is used to complete the PLL. The PLL will generate a cleaned output signal which is in phase to the input. The highest output frequency for CDCM7005 is equal to the VCO/VCXO frequency.

This is not the case for the LMK04002. This device has 2 cascaded PLLs. The 1st PLL with external VCO/VCXO is used to clean the reference/input signal, whereas the 2nd PLL uses an internal VCO (high frequency) to synthesize the output frequencies. This concept allows you to use a VCO/VCXO with lower frequency, which is in general cheaper than higher frequencies.

2. the mentioned VCXO is not able to meet your phase noise requirements at 1kHz offset. (see table 8 and 9 in d/s).

5. http://www.ti.com/tool/cdc-cdcm7005-calc

Regards,

Julian

Hi Julian,

Nice to hear from you! Kindly clarify the following terms, it will help me to understand about the PLL & its basics:

1. What is loop bandwidth ?

2. impact of loop bandwidth on the Final phase noise & jitter ?

3. Is there any application note to understand the basics of PLL ?

4.Application note for the detailed working of LMK4002 & CDCM7005 ?

Regards,

Rajesh.S

Hello Rajesh,

Please have a look in the "module description" of the CDCM7005 PLL sim Tool, which i send you. Most of the the PLL internals are described and explained. In this tool you can also "play" with the loopbandwidth to actually see the impact in the phase noise profile.

4. for more information of CDCM7005, please have a look in the application section in the datasheet and here: http://www.ti.com/product/cdcm7005#doctype1

for more information of the LMK04002 have a look in the application note section as well: http://www.ti.com/product/lmk04002#doctype1

Regards,

Julian

Hi Julian,

Thanks for the reply. I had tried both the clock tools(LMK4002 & CDCM7005 lab view version), in that I have the following query's:

Query Regarding CDCM7005 Lab view version(http://www.ti.com/lit/sw/scac059a/scac059a.zip):

1. Where should I enter the loop bandwidth ?(there is no specific block is available for these in the tool)

2. Pll phase noise completely depends on the VCXO phase noise not the reference clk phase noise(since I had used the AOCJY-20.000MHz OCXO as a reference CLK oscillator and 800MHz VCXO from the silicon labs.

Hi,

I am looking for the low phase noise & jitter cleaner for my DAC & ADC clocking applications, I have some specifications, kindly suggest the right part for my application:

Requirements:

The following clock signals need to be generated:

DAC sampling clock:800MHz(LVPECL) DAC part number: AD9736

ADC-1 sampling clock: 200MHz(LVPECL) ADC part number: ADS5474

ADC-2 sampling clock: 400MHz(LVPECL) ADC part number: ADS5474

FPGA data clock: 20MHz(LVCMOS) FPGA part number: XC7k410T(kintex-7 FPGA)

L-Band ref clock: 20MHz(LVCMOS)

Available clock sources:

High stability OCXO: 20MHZ(HCMOS with 0.01ppm) OCXO part number: AOCJY-20.000MHZ-E

External clock: 20MHz(sine wave with 0.5V to 5V peak to peak)

We have already used the following two parts from TI in our previous projects separately: CDCM7005(clock distribution for the ADC), LMK4002(clock  distribution for the DAC)

Now we have the following two plan's for the clock scheme:

Clock scheme-1 Using CDCM7005:

while using CDCM7005 OCXO(AOCJY-20.000MHZ-E) shall be connected  as a REF CLK & a VCXO of 800MHz 571AEC000107DG from silicon labs(for 800MHZ part ordering information will be changed these part shall support upto 260MHz) will be connected to the VCXO_IN pins. All other frequencys will be generated from these scheme, While using these scheme we have the following constrains:

1.VCXO of 800MHz currently not available in our office(it needs to be ordered newly)

2. Phase noise of 800MHz VCXO considerably very poor( because of high frequency)

Qerry releated to these scheme:

At any case my OCXO phase noise should dominate , to achieve these specifications what should be the effective loop bandwidth of CDCM7005 & other settings?

Clock scheme-2 Using LMK4002:

while using LMK4002 OCXO(AOCJY-20.000MHZ-E) shall be connected  as a REF CLK & a VCXO of 100MHz (CVHD-950X-100) shall be connected to the OSC_in pins

PLL-2 is locked for the 1600MHZ remaining all other frequency's will be generated from these configuration.

Query related to these configuration:

While comparing the phase noise of OCXO, VCXO, internal VCO of these scheme the order is like these OCXO>VCXO> Internal VCO.

1. In order  to acheive the best phase noise at the output what should be my PLL-1 Loop BW & PLL-2 Loop BW ?

General Query:

By comparing both the clock schemes which clock scheme will provide best performance & reason for the same ?

At the same time I had tried both the clock design tools of the TI:

http://www.ti.com/lit/sw/scac059a/scac059a.zip for CDCM7005 labview version

http://www.ti.com/lit/sw/snac013/snac013.zip  for LMK4002

Regards,

Rajesh.S