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LMK00308 EVM

1886332
Expert 1325 points

Hi,

Two Questions:

1. I am entering a Sin 100MHz -2dbm and I get a very bad output and about 20% duty cycle, why is that?

2. When I power up to 0dbm I get 1.5V peak to peak in REFout, why is that? I want to get 3.3V p2p.

Thanks,

  • 0
    TI__Mastermind 32575 points

    1. Which input port are you driving (CLKin0 or 1 or OSCin)?  Are you using the default EVM configuration or did you modify it (if so, please send modified component values).  

    What output bank format is configured on the output measured?  While you measured the output (pair), how are the other outputs connected?  The other outputs should be either terminated or disconnected from the trace to avoid signal integrity issues that can arise when any driven output trace is left unterminated. 

    2. The output swing will be lower due to the voltage divider formed by the CMOS driver output resistance (50 ohms internal) and input resistance of your scope (50 ohms I assume). Also, the limited output current drive capability of the CMOS driver will also reduce the swing.  To get full 3.3 V CMOS swing, make sure the output loading (receiver input) has a high resistance. 

    Regards,

    Alan

  • 0 in reply to Alan O
    Expert 1325 points

    Dear Alan,

    I am driving CLKin0. I did conifuration following the EVM datasheet for Single ended, AC coupled input.

    The output measured is REFout. The other outputs are just not connected.

    Thanks,

  • 0 in reply to 1886332
    Expert 1325 points

    Dear Alan,

     

    Kind Reminder.

  • 0 in reply to 1886332
    TI__Mastermind 32575 points

    Thanks for the reminder.

    The differential input pins (CLKinX+ and CLKinX-) are self-biased with internal bias resistors (~1.1 V and ~1.4 V, respectively).  The offset voltage of ~0.3 V was intentionally designed as fail-safe mechanism to avoid input switching/chattering when the differential input pins are floating.  This sets the inputs to a low logic state when the differential input pins are floating.

    Since you're using the input interface circuit from Fig. 3 in the datasheet (intended for faster LVCMOS input signals), the coupling capacitors will preserve the input offset voltage and cause the switching threshold to be offset from the 50% level of the sine wave input, leading to the duty cycle distortion.  The duty cycle distortion is made worse due to the slow edge/slew rate of the 100 MHz, -2 dBm sine wave input. 

    While increasing the input slew rate may help reduce the duty cycle distortion, we should be able to eliminate the problem using the input interface circuit shown below.  In this case, the 50-ohm resistor terminated across the differential input pins will eliminate the input offset voltage and the DC blocking caps will preserve the internal bias voltage at the inputs.  Please note that additive jitter and noise floor will degrade at lower slew rates according to the typical performance plots in the datasheet.  It is recommended to have input slew rate of 3 V/ns to achieve best possible performance.

    Regarding the attenuated output swing, hopefully the explaination in my previous post was clear enough. 

    Best regards,

    Alan