LOOKING FOR THE LOW PHASE NOISE &JITTER CLEANER FOR THE CLOCK DISTRIBUTION

Hi,

I am looking for the low phase noise & jitter cleaner for my DAC & ADC clocking

applications, I have some specifications, kindly suggest the right part for my application:

Requirements:

The following clock signals need to be generated:

DAC sampling clock:800MHz(LVPECL) DAC part number: AD9736

ADC-1 sampling clock: 200MHz(LVPECL) ADC part number: ADS5474

ADC-2 sampling clock: 400MHz(LVPECL) ADC part number: ADS5474

FPGA data clock: 20MHz(LVCMOS) FPGA part number: XC7k410T(kintex-7 FPGA)

L-Band ref clock: 20MHz(LVCMOS)

Available clock sources:

High stability OCXO: 20MHZ(HCMOS with 0.01ppm) OCXO part number: AOCJY-

20.000MHZ-E

External clock: 20MHz(sine wave with 0.5V to 5V peak to peak)

We have already used the following two parts from TI in our previous projects separately:

CDCM7005(clock distribution for the ADC), LMK4002(clock  distribution for the DAC)

Now we have the following two plan's for the clock scheme:

Clock scheme-1 Using CDCM7005:

while using CDCM7005 OCXO(AOCJY-20.000MHZ-E) shall be connected  as a REF CLK &

a VCXO of 800MHz 571AEC000107DG from silicon labs(for 800MHZ part ordering

information will be changed these part shall support upto 260MHz) will be connected to the

VCXO_IN pins. All other frequencys will be generated from these scheme, While using

these scheme we have the following constrains:

1.VCXO of 800MHz currently not available in our office(it needs to be ordered newly)

2. Phase noise of 800MHz VCXO considerably very poor( because of high frequency)

Qerry releated to these scheme:

At any case my OCXO phase noise should dominate , to achieve these specifications what

should be the effective loop bandwidth of CDCM7005 & other settings?

Clock scheme-2 Using LMK4002:

while using LMK4002 OCXO(AOCJY-20.000MHZ-E) shall be connected  as a REF CLK & a

VCXO of 100MHz (CVHD-950X-100) shall be connected to the OSC_in pins

PLL-2 is locked for the 1600MHZ remaining all other frequency's will be generated from

these configuration.

Query related to these configuration:

While comparing the phase noise of OCXO, VCXO, internal VCO of these scheme the order

is like these OCXO>VCXO> Internal VCO.

1. In order  to acheive the best phase noise at the output what should be my PLL-1 Loop

BW & PLL-2 Loop BW ?

General Query:

By comparing both the clock schemes which clock scheme will provide best performance &

reason for the same ?

At the same time I had tried both the clock design tools of the TI:

http://www.ti.com/lit/sw/scac059a/scac059a.zip for CDCM7005 labview version

http://www.ti.com/lit/sw/snac013/snac013.zip  for LMK4002

Regards,

Rajesh.S