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CDCE72010 register configuration

Inaki Val
Prodigy 10 points
Other Parts Discussed in Thread: CDCE72010

Hi,

 I am trying to configure a CDCE72010 for using an external reference clock of 10 MHz (coming from instrumentation) connected to SEC_REF. It also uses a 491.52 MHz VCXO for clock generation. The register values are the following:

682C0290
68000021
83800002
68000003
E9800004
68000005
68000006
83400017
68000098
68000049
0BFC07CA
8000040B
0000180C

Charge pump current = 2.2 mA

R = 1 , N = 125, M = 768 and P = 8

The PLL filter is configured as:

C1: 100nF
R2: 4k7
C2: 22uF
R3: 160ohms
C3: 100nF

The PLL does not lock. The excel loop filter simulator gives a closed loop bandwidth of 67 Hz for an update frequency of 80 kHz.

Is something wrong?

Thanks in advance

  • 0
    TI__Expert 3985 points

    Hi Inaki,

    the device settings appear to be correct  for a certain extend . I have a couple of points I would like to check with you. Are you feeding the CDCE72010 with a 10MHz LVCMOS input and providing an appropriate external termination? Also what is the signaling level of the VCXO single ended or LVPECL?

    I am asking the previous questions because it seems like you selected a LVCMOS input and you did not select the internal termination. Also, it looks like you are using an LVPECL VXCO and you are using the VCXO_IN- pin to feed out the VCXOVBB bias voltage. This combination is not possible.

    Thanks and best regards,

    Leandro