Hi,
The customer use the PFD = 61.44MHz and found the output frequency is not stable; they reduce the PFD and find the chip work correctly.
So in the CDCE706, what is the maximum PFD the chip can support? how the cusotmer can know the optimized phase margin/charge pump/loop filter bandwidth value? Or it is a black box to customer? Thanks!
"All three PLLs are designed for easiest configuration. The user must define only the input and output frequencies
or the divider (M, N, P) setting. All other parameters, such as charge-pump current, filter components, phase
margin, or loop bandwidth are controlled and set by the device itself. This assures optimized jitter attenuation and
loop stability."
