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CDCM61001 LVCMOS output

XIAOLIANG TAN
Prodigy 80 points

Other Parts Discussed in Thread: CDCM61001

Dear Expert,

       I am trying to buy a CDCM61001 to generate a 1.2 V clock. In the cadence simulation, I use a voltage divider (650 ohm => output => 300 ohm to gnd) at the end of my Transmission line. The load of the driver is around 3 pF, may I know that whether the real chip could support this? 

       I plot the current in my driver source, it needs a  +- 30 mA (peak- peak). Which definitely are much larger than 100 uA (IOH, IOL). 

       But I checked the testing structure of the CDCM61001, it can drive a 5 pF at 250 MHZ. 

       Could you give me some suggestions? 

        Thanks

Xiaoliang

  • 0
    TI__Expert 3985 points

    Hi Xiaoliang,

    I run some simulation based on the IBIS model, I attached the schematic. Unfortunately the CDCM61001 LVCMOS output is not able to generate a 1.2V LVCMOS signal after the resistor divider. If you can accept a clock with 0.8V amplitude, I can suggest you to use an LVPECL output, AC couple it and provide the bias voltage.

    Best regards,

    Leandro