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CDCE925 Powerdown

Mitch Gallaher
Prodigy 20 points

Other Parts Discussed in Thread: CDCE925

I've been using the CDCE925 as a clock source and need to be able to turn off the PLLs. Ideally, I would like the PLL outputs disabled by default during power on to prevent noise to the board and any irregular behavior of the DUT when the PLL signal is not being used. Unfortunately, it seems the power down bit cannot be set at 0 by default. Is there any other way to shut down the part after power on other than rewriting this register after every power cycle?

Thanks,

-Mitch

  • 0
    TI__Mastermind 20900 points

    Hello Mitch,

    during power up you can pull S0 to low. This would disable the outputs (tristate) in the default CDCE925 register settings (see picture below).

    If you reprogram the EEPROM anyway, you might be able to change this by reprogramming the "control Terminal setting" (page 10 from d/s). You will need to change the output state definition (Register bits: Yx_STx)

    best regards,

    Julian

  • 0 in reply to Julian Hagedorn
    Prodigy 20 points

    Julian,

    Thanks for the response and sorry for the late reply. Someone had pointed out the output disable states after I posted this, but that appears to be a good solution to my problem. Thanks for the suggestion!

    Cheers,

    -Mitch