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CDCE18005 Output Divider Programing - Data Sheet

John Leahy
Prodigy 10 points
Other Parts Discussed in Thread: CDCE18005, LMK00306, CDCE62005, CDCLVD1204, LMK01801

I want to supply a 500 MHz LVDS reference clock  and generate 5 LVDS clocks and 1 LVCMOS clock, but all at 125 MHz.

A Precsaler vale of 2 and an Integer Divider value of 2 should do that, but that combination is not included in the Output Divider Settings Table.

Is this a valid setting that was left out of the Table and if so, will it generate what I have described?

  • 0
    TI__Intellectual 950 points

     Hi John,

    your finding is right, the CDCE18005 does not support a divider setting of 4 for all outputs (5 x LVDS and 1 x LVCMOS). Div-by-4 is valid for the LVDS outputs but not for the LVCMOS output at the same time.

    If you can implement a 2-chip solution, the CDCE62005 (Div4 and LVDS/ LVCMOS output) and LVDS buffer like CDCUN1208 (1:8), LMK00306 (1:7) or CDCLVD1204 (1:4) may work as well.

    Also you might have a look to  the LMK01801 with Divider option and LVDS and LVCMOS outputs.

    Regards,

    Georg.