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CDCM6208V1

fearghal rudden
Intellectual 480 points

Other Parts Discussed in Thread: CDCM6208V1, CDCM6208

Hi, 

I have received a development board with CDCM6208V1 clock generator and am currently experiencing problems if you guys could help?

I am operating the device in pin mode with the following specifications:

SI_MODE

10

Pin[4:0]

0x1B

fin (PRI_REF) (TYPE)

n/a

fin (SEC_REF) (TYPE)

25MHz (Crystal)

f(PFD)

25MHz

f(VCO)

2500Hz

fout(Y0) (TYPE)

100MHz (PECL)

fout(Y1) (TYPE)

100MHz (PECL)

fout(Y2) (TYPE)

250MHz (PECL)

fout(Y3) (TYPE)

250MHz (PECL)

fout(Y4) (TYPE)

100MHz (HCSL)

fout(Y5) (TYPE)

100MHz (HCSL)

fout(Y6) (TYPE)

125MHz (HCSL)

fout(Y7) (TYPE)

66.67MHz (HCSL)

 

I am not seeing any clocks on the outputs of the device. I have the device powered correctly and the pin mode and SI mode is as specified in the table. My input clock looks fine when probed on the sec_refp pin but on the sec_refn pin the signal is distorted and attenuated. I am hoping that this issue is to do with the crystal I have selected as I realize I did not match the required specifications in the datasheet.

 

The datasheet recommended a crystal with a drive level of at least 200 uW, 70 ohm ESR (for 25 MHz) and 8 pF load capacitance. I have placed a crystal with a drive level of just 100 uW maximum, 30 ohm ESR and 20 pF load capacitance.

 

Can you confirm that this is the issue? Could you also confirm if I replace the crystal with one that has a higher drive level then I should be able to get the device operating?

 

Thank you,

 

Fergs

  • 0
    Intellectual 390 points

    Hello Fergs,

    what you see on sec_refn-pin is ok, but it`s recommended to change the crystal, but this may not solve the issue with the outputs.
    So let us check the following setting on your device:

    In pin-mode some other configurations are also important, specially pin and VDD settings.
    Please take a look at your board an confirm that the following settings are done on the board.

    PDN  (pin 43)        - has to be high to activate the device
    RESET (pin 44)    - select the voltage in "pin-mode" - "1" =2.5V / 3.3V - "0" = 1.8V (in pin-mode we can only use one overall voltage level)
    REF_SEL (pin 6)  - has to be high to select the sec_ref-input (where the crystal is connected)

    and also every VDD-pin has to be powerd, all pins with the same voltage level, (1.8V , 2.5V or 3.3V)

    VDD_PRI_REF (pin 7)
    VDD_SEC_REF (pin 10)
    VDD_Y0_Y1 (pin 13 & pin 18)*
    VDD_Y2_Y3 (pin 19 & pin 24)*
    VDD_Y4 (pin 27)*
    VDD_Y5 (pin 30)*
    VDD_Y6 (pin 31)*
    VDD_Y7 (pin 34)*
    VDD_PLL1 (pin 37)
    VDD_PLL2 (pin 38)
    VDD_VCO (pin 39)
    DVDD (pin 48)

    Please check these settings and may you can share with us a schematic of how the device is implemented in the development-board to give us a better understanding.

    *only VDD_OUT supply-pins can be pulled to GND to disable output-buffer and save current 

    Best Regards
    Michael

  • 0 in reply to Michael Wagner (Intern)
    Intellectual 480 points

    Hi Michael,

    Thanks for your help on this, i'm a bit stumped.

    In relation to the settings you have highlighted, I have made the following configurations on my design:

    PDN  (pin 43)        - Unconnected. The datasheet states that If the supply ramp time for DVDD, VDD_PLL1, VDD_PLL2, VDD_PRI, and VDD_SEC are faster than 50 ms from 0 V to 1.8 V, no special provisions are necessary on PDN; the PDN pin can be left floating as it is internally pulled high. All pins are supplied by the same 3V3 source, with VDD_PLL2 and VDD_VCO filtered.
    RESET (pin 44)    - Unconnected. Again, the datasheet indicates that the pin is internally pulled to DVDD.
    REF_SEL (pin 6)  - this pin is pulled high to select the sec_ref-input
    All VDD pins are powered except for VDD_PRI_REF(pin 7) which is tied to GND as it is stated that it can be set to 0V if the primary input is not used, which it isn't.

    I have attached a pdf of the schematic if you can see anything out of place:

    7607.CDCM6208_Implementation.pdf

    I have some other development boards that I hope to have at the same level for testing by tomorrow in the hope that I can either reproduce the failure or find out if the failure is specific to this board.

    Thanks again Michael,

    Best Regards,

    Fearghal

  • 0 in reply to fearghal rudden
    Intellectual 480 points

    I've brought up a second development board and the result is the same as the first.

    I then tied the PDN and RESET pins to 3V3 via pull-up resistors and changed the crystal to one with a greater drive level. The result has been the same. The SYNC signal is also set at 3V3 at power up.

    I will look into the pin mode configurations to see if an adjustment to the pin mode selections could make a difference but so far all I am seeing is a 3V3 signal on the output 

  • 0 in reply to fearghal rudden
    Intellectual 390 points

    Hello,

    sorry for my delay, your settings are all right, but there is a mistake in the datasheet on page 44 in the footnotes, it will ba changed very soon to the following text:
    "If the system only uses a XTAL on the secondary input, REF_SEL should be tied to VDD. The primary and secondary input stage power supply must be always connected."
    So if VDD_PRI_REF (pin 7) is not Powerd the SEC_REF will also not work in pin mode.
    Can you pleas change this and confirm the setting.
    But it`s still recommanded to change the Crystal, because if the drive level is to low ,the device could break the crystal in long term use.

    Best Regards

    Michael

  • 0 in reply to Michael Wagner (Intern)
    Intellectual 480 points

    Hi Michael,

    No problem. I was able to disconnect VDD_PRI_REF from GND and power it from 3V3. So far I have seen no improvement. I had used the original settings I had mentioned in my first and second post.

    The new 25MHz crystal is oscillating so I presume the device is operating but the clock status output signal remains low. I have also tried to pull the following signals to 3V3: RESET, PDN and SYNC. I have connected REF_SEL now to 3V3 directly instead of through a pull up resistor.

    Can you confirm if the RESET, PDN and SYNC pins need to be pulled up to 3V3 in my design or can the first 2 be left floating and internally pulled up? Also can REF_SEL be tied to 3V3 directly?

    Best Regards,

    Fearghal 

  • 0 in reply to fearghal rudden
    Intellectual 480 points

    I am still having issues with getting this device up and running.

    I probed each pin on the device and have measured the following values on one of the development boards that has not been re-worked. So the  VDD_PRI_REF is connected to GND in this setup and matches the previously attached pdf in my first post.

    Would you be able to confirm if the inputs to the device are as expected though?

    The device should be in pin mode and the control pins [4:0] should be configured to 0x1B as stated before

    Pin No. Pin Name Reading
    1 SIMode0 GND
    2 P1 3V3
    3 P2 GND
    4 P3 3V3
    5 P4 3V3
    6 REF_SEL 3V3
    7 PRI_VDD GND
    8 PRI_CLK GND
    9 PRI_CLK GND
    10 SEC_VDD 3V3
    11 SEC_CLK 25Mhz_Clk
    12 SEC_CLK 25MHz_Clk
    13 VDD_Y0/Y1 3V3
    14 Y0_P 1.6V
    15 Y0_N ?
    16 Y1_N 3V3
    17 Y1_P 1.6V
    18 VDD_Y0/Y1 ?
    19 VDD_Y2/Y3 ?
    20 Y2_P 1.6V
    21 Y2_N 3V3
    22 Y3_N 3V3
    23 Y3_P ?
    24 VDD_Y2/Y3 3V3
    25 Y4_N 3V3
    26 Y4_P 3V3
    27 VDD_Y4 3V3
    28 Y5_N 3V3
    29 Y5_P 3V3
    30 VDD_Y5 3V3
    31 VDD_Y6 3V3
    32 Y6_P 3V3
    33 Y6_N 3V3
    34 VDD_Y7 3V3
    35 Y7_P 3V3
    36 Y7_N 3V3
    37 VDD_PLL1 3V3
    38 VDD_PLL2 3V3
    39 VDD_VCO 3V3
    40 Reg_Cap 1.6V
    41 ELF 0V
    42 SYNCN 3V3
    43 PDN 3V3
    44 RESETN/PWR 3V3
    45 P0 3V3
    46 STATUS0 GND
    47 SIMODE1 3V3
    48 DVDD 3V3

    The question marks are areas where it was difficult to probe on the development board.


    I am having issues with the reworked board now that I am working on but, initially, after I changed the Primary VDD pin from GND to 3V3, no change was seen on the clock outputs.

    Is there a sequence that needs to be implemented on the SYNC, PWR and PDN pins? It is not clear in the datasheet if there are timing restrictions apart from when powering up the device power pins. The data sheet states on page 60:“0 -> Force synchronization” and “1 -> Exists synchronization”, The syncn pin stays high on power on for our device, is this ok?

    Best Regards,

    Fearghal

  • 0 in reply to fearghal rudden
    Intellectual 390 points

    Hello,

    so i can confirm that the PDN pin is internally pulled to VDD, this could be a problem if the power-up ramp is too slow, so the device will not calibrate correctly.
    The SYNC pin is also internally pulled high, but in Pin -Mode the RESET_PIN select the supply voltage to the device (high for 3.3V).

    It is important to pull VDD-PRI_IN to 3.3V.(even when it`s not used)

    There is a sequence to recalibrate the device: power up the device and keep PDN low after the device is powerd release the PDN pin, if the device now works fine add a 100nF - 1µF cap to GND to slow the device startup. (if the device is on and PDN is released it will consume ~380mA)

    Please also take a look at the output termination.

    Best Regards

    Michael

  • 0 in reply to Michael Wagner (Intern)
    Intellectual 480 points
    Hi again,
    Sorry for my delay. I implemented the original change you recommended Michael and the clocks are now locked and I am seeing the desired output on all of the PECL pins. I had to change the termination on the HCSL pins to see an output but they now appear to be working, which is great.

    So my original settings are the same, except now I pull VDD-PRI_IN to 3.3V and I have added 50 ohm termination resistors to the HCSL outputs. Thanks again for your help with this. I have some further queries on this matter if you can help me further?

    I have been working with the C6678 DSP and the clock pins are defined as LJCB pins:
    In the Keystone Devices Hardware Design Guide it states the following for C66x Device reference clocks:
    "All differential clock input buffers are low jitter clock buffers (LJCBs). These input buffers include a 100 Ω parallel termination (P to N) and common mode biasing (unless otherwise specified). Because the common mode biasing is included, the clock source must be AC coupled (except where noted in this document and data sheet). Low voltage differential swing (LVDS) and LVPECL clock sources are compatible with the LJCBs"
    and

    "Note that all LJCB and LVDS differential input clock buffers contain a 100 Ω internal termination resistor (no external resistor is required)"

    On another post in the C6000 Multicore DSP section, it is confirmed that the LJCB can interface with HSCL drivers with just the AC coupling.  This is the same connection needed by the LVDS:

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/207202.aspx

    Do you know why the HCSL pins did not output a clock when the DSP should have internal termination?

    Best Regards,
    Fearghal

  • 0 in reply to fearghal rudden
    Intellectual 390 points

    Hi Fearghal,

    for  HSCL you will need the 50 Ohm to GND. this will provide a controlled path to GND, which will allow the internal transistors to open.
       
    I added an exaple:

     Ignore the 0Ohm resistors and connect the DSP were the SMA connectors are shown, also put the AC coupling next to the DSP-input.

    Best Regards
    Michael

  • 0 in reply to Michael Wagner (Intern)
    Intellectual 480 points
    Hi Michael,
    I probably should have questioned it before implementing the design but I had presumed the HCSL configuration in the CDCM6208 datasheet was an example of a DC coupled set up only.
    When browsing the e2e forums, it was indicated that the HCSL signals could be AC coupled to the clock pins on the C6678 DSP in a similar fashion to LVDS signals. This confused me and led me to believe that the 50 ohm resistor was not necessary.

    I currently only have the HCSL pins tied to ground with no coupling capacitors and my board seems to work. I will make sure to include these capacitors as well though.

    Thanks again for your help
    Best Regards,
    Fearghal