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lmk04906 EVAL (v1.) does not generate max. clock-freq. output

Walter Gerhard
Prodigy 40 points
Other Parts Discussed in Thread: LMK04906, CODELOADER, CLOCKDESIGNTOOL

Hello,

I evaluate a lmk04906 (v1.0) board with latest codeloader under winXP.

I select the lmk04906B device from the list.

Actually it works fine but if I set the clk_div to "1" no clk-output is generated (should be about 2.4-2.6GHz).

Setting this value to "2" it works and a clk-freq of about 1.2-1.3GHz is generated.

Tested all available configs.

 

Furthermore:

What is the techn. difference of the Eval-boards "lmk04906" (v1.0) and "lmk04906B" ?

Is there a description of changes and a bug-list?

 

Any ideas? Thanks a lot. Walt.

 

  • 0
    TI__Mastermind 28550 points

    Hello Walt,

    There is only LMK04906B, the B is the only IC version.  (There never was an A).

    Analog delay only works to max 1536 MHz, is analog delay on?  This could explain no clock output.

      - What clock output format are you using?

      - What are you testing for clock output with?  A high speed scope with high speed probe or spectrum analyzer?

    73,

    Timothy

  • 0 in reply to Timothy T
    Prodigy 40 points

    Hello Timothy,

    As I figured out there is a difference between the 2 EVAL-boards, Eval "LMK04906 (v1.0)" and Eval "LMK4906B". The chip is the same but obviously other components like onboard oscillators are beeing used. 

    I ordered an Eval "LMK4906B" from the ti store and got a the older version "LMK04906 (v1.0)". Why? I dont know...

    The problem is that there is no documentaion of the older Eval, only for the B-version. The codeloader mode examples (122.88MHz) with the predefined register settings are also made for this B-release.

    Other than I posted before the board was not correctly operating as the PLL are not locked that I have not determined at first. Herewith are connected the problems with generating the full clk output. The reason is that the onboard osc. is a 25MHz and not a 122.88MHz VCXO. 

    I could get it locked now but the phase noise strongly depends from my own determined PLL settings. It even generates a clear (max.) 2.7GHz locked clk output that is beyond the techn. spec. of max. 2.6GHz.

    What I need is a full documentation including schematics of this (older) Eval board in the same style as for the B-version. I need to know the PLL loop parameters and what is soldered onto this board, finally I need the correct PLL loop settings for this version.

    Finally, why is the older Eval board shipped from TI and not the clear labeled and ordered B-version? (I ordered this board in Nov./Dec. 2012).

    Thanks, Walt.

    PS: I measure on the clk_0_out with LVPECL setting (max) and a 50Ohm-SA, the other port is terminated with a 50Ohm load.

     

     

  • 0 in reply to Walter Gerhard
    TI__Mastermind 28550 points

    Hello Walt,

    My understanding is you have two boards with 25 MHz VCXOs?  I've checked and the new version of the board is the one with the 25 MHz VCXO.  This needs to be updated in the instructions.  I will post you on this progress.

    Please find attached a .mac file for the LMK04906 to load into codeloader.

    I'll be working to determine the other questions, in the meantime, you now can get a clock output in /1 mode?

    73,

    Timothy

    6683.lmk04906_25MHzVCXO_with50MHz_doubler.zip

  • 0 in reply to Timothy T
    Prodigy 40 points

    Hello Timothy,

    I have only one board, that with the 25MHz Osc. The EVAL Board Operation Instructions (SNAU126, June 2012) reports and describe

    a 122.88MHz CVHD-950-122.88MHz. On the cover page of this docu. you can see the EVAL board and a silkscreen printing "LMK04906 Eval Board 2011-12-06 v1.0". 

    Exactly the same print as on my board with the 25MHz Osc.

    Obviously there are 2 different (!) boards sold by TI !

    Could you please verify what is the history? What is the latest version? Whats about the documentation? Pretty simple questions...

    I am confused about the difference of my EVAL board and the official documenation.

    Furthermore I got the PLL2 locked as I figured out that I have the 25MHz version, but the lock behaviour is strange, not repeatable and not reliable.

    I have often to click several buttons before it locks. To investigate the PLL2 loop dynamics I need the right and reliable documentation for that board.

    At the moment I also dont know the PLL2 loop filter data that are soldered on the board. The docu (schematics) describes this, but for the 122.88MHz Osc., which cannot be the same for an another ref. freq. of 25MHz.

    When can you get this documentation for the 25MHz version?

    Is there a picture of the phase noise of the PLL2 VCO or a SW for PLL simulations? I need this to determine the PLL-bandwidth and loop parameter as I am going to feed a standard 100MHz Osc. to the PLL2 and need a PLL time/freq. simulation.

    Thanks, Walter.

     

  • 0 in reply to Walter Gerhard
    TI__Mastermind 28550 points

    Hello Walter,

    I've got some answers for you below...

    Walter Gerhard said:
    Could you please verify what is the history? What is the latest version? Whats about the documentation? Pretty simple questions...


    Early testing of LMK04906 was with 122.88 MHz, however we released with 25 MHz VCXOs and have made a mistake on not doing all needed updates with this release.

    Walter Gerhard said:

    Furthermore I got the PLL2 locked as I figured out that I have the 25MHz version, but the lock behaviour is strange, not repeatable and not reliable.

    I have often to click several buttons before it locks. To investigate the PLL2 loop dynamics I need the right and reliable documentation for that board.


    I have locked at tested an LMK04906 eval board with the settings in this attached mac file: lmk04906_25MHzVCXO_with50MHz_doubler, 2013-02-01.mac

    With this attachment, you can load the .mac and the device should lock and operate as desired.  When testing board, turn off or terminate unused clock outputs.

    However, it does appear that you could have some locking issues due to PLL1 loop filter...  see next.

    http://e2e.ti.com/cfs-file.ashx/__key/communityserver-discussions-components-files/48/2626.lmk04906_5F00_25MHzVCXO_5F00_with50MHz_5F00_doubler_2C00_-2013_2D00_02_2D00_01.mac

    Walter Gerhard said:
    At the moment I also dont know the PLL2 loop filter data that are soldered on the board. The docu (schematics) describes this, but for the 122.88MHz Osc., which cannot be the same for an another ref. freq. of 25MHz.


    This seems to be another issue, that when the VCXO was updated to 25 MHz, the loop filter values were not changed.  I checked the R2 value of PLL1 and PLL2 loop filter and found them to be the same as in the eval board documentation.  That is PLL1 R2 = 39k and PLL2 R2 = 620 ohms.  Using the assumption the caps are the same also...

    For PLL1, according to clock design tool sims:
    With a 100 uA charge pump current: phase margin is 32.2 degrees and loop bandwidth is 60 Hz
    With a 400 uA charge pump current: phase margin is 17 deg and has a loop bandwidth of 131 Hz.

    I can get the PLL to lock with either setting, of course the 100 uA would be more stable (the .mac file above has 400 uA charge pump for PLL1, you may try decreasing this by right-clicking on PLL1 charge pump current value on PLL1 tab.  You can increase by left-clicking on PLL1 charge pump current value on PLL1 tab).
       > However, with the low charge pump current of 100 uA and the loop filter parameters, the PLL1 DLD will not indicate because the charge pump will be required to operate greater than the maximum PLL1 DLD window size of 40 ns.



    Walter Gerhard said:
    When can you get this documentation for the 25MHz version?


    I do not have a timeline yet, but will be working to address this.

    Walter Gerhard said:
    Is there a picture of the phase noise of the PLL2 VCO or a SW for PLL simulations? I need this to determine the PLL-bandwidth and loop parameter as I am going to feed a standard 100MHz Osc. to the PLL2 and need a PLL time/freq. simulation.


    Please see the Clock Design Tool software, clicking on this clockdesigntool link will take you to a page where you may design the loop filter for the LMK04906.  There are also several training videos on this website describing the use of the software.

    I recommend re-designing the PLL1 loop filter, here is a design I did to match the 12 Hz/50 degrees phase margin originally intended for PLL1.

    C1 = 39 nF, C2 = 270 nF, R2 = 12 kohm; PDF = 1000 kHz, CP = 0.4 mA, VCXO = 25 MHz.

    ---

    Other than the updated documentation, are there any other questions or design issues with the LMK04906 I can help you with?  I apologize for this error, you have every right to be upset about this.

    73,

    Timothy

  • 0 in reply to Timothy T
    Prodigy 40 points

    Hello Timothy,

    thanks a lot for the given explanations. I will go with it and come back to report.

    open issues:

    - could you please provide a datasheet or description of the 25MHz VCXO  ?

    - Later I would like to substitute this VCXO with an external XO with a SMA connection, is this possible?

    ---> I have to solder a SMA end launch jack to the board because they are not provided. How to disable the VXCO? Does it need to be removed from the board?

    Thanks, Walter.  

  • 0 in reply to Walter Gerhard
    TI__Mastermind 28550 points

    Hello Walter,

    Walter Gerhard said:
    - could you please provide a datasheet or description of the 25MHz VCXO  ?

    Epson VG-4231CA, GRC type.  Datasheet is at: http://www.eea.epson.com/portal/pls/portal/docs/1/1545709.PDF

    Here was what I characterized the Kvco on my board, ~4.5 kHz/V:

    Walter Gerhard said:

    - Later I would like to substitute this VCXO with an external XO with a SMA connection, is this possible?

    ---> I have to solder a SMA end launch jack to the board because they are not provided. How to disable the VXCO? Does it need to be removed from the board?

    If you use just an XO, then you will run in PLL2 only mode...

    This is possible, all you need to do is...

    1) disable power from the VCXO by removing R123:

    2) Place switch capacitor in proper position to get signal from SMA to LMK04906 OSCin.  (C12 --> C13).

    73,

    Timothy