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CDCM6208 - to High IF sampling ADC

veerasamy v
Prodigy 180 points
Other Parts Discussed in Thread: CDCM6208

In CDCM6208 datasheet it is mentioned that, while using this device to clock ADC, there will be SNR degradation when the IF frequency is above 100MHz. Our IF is around 160MHz. Is it recommendable to use CDCM6208 in this case? Or is the SNR degradation common for all clock generators? We need to provide 110MHz clock to ADC.

  • 0
    TI__Intellectual 950 points

    The 100MHz IF frequency or below was used to compare the SNR performance when using the CDCM6208 vs. a very clean lab source.  A slightly higher IF frequency may show similar good results, however, the total answer depends on how many bits the ADC is and the SNR of the ADC. I’ve attached a paper that explains this in more detail.

     8004.Jitter_in_the_time_domain_Texas Instruments.pdf

    You may want to use an eval board to see what performance you will get. The lower the RMS phase noise, the better, so using a higher frequency input reference to the 6208 can improve the RMS jitter and the SNR as well.

    Regards, Georg.