LMK03002C not Lock

Hi Eugene,

Your register format does not seem corret. The last four bits definte the register address. For example, register R4, the last four bits should be 0100. Pls use CodeLoader to generate the required register values.

Hi Noel,

Thank you for your response. Yes, I showed the registers without the address bits, but I load them.

I have two boards.  On a single board, the chip works.I n the second, the chip was stable work, while for some reason stopped locking.

I'm trying to understand what led to this.

I see, that common voltage level of then OSCin - 2.36V on board dead.  On working board - 1.5.

Also, on the working board, voltage Vcpout rises from 0V to 1.4, only after loading registers. On the not working board - Vcpout risesfrom 0V to 0.75V  immediately after power up.

Hi Eugene,

A couple of things to try.

First of all, make sure OSCin are AC-couple and LDObyp1,2 are properly decoupled.

Set PLL_MUX to "Digital LD Active High", if it is locked, you should see a stable logic HIGH at LD pin. If you see a different result, go to next  step.

Set PLL_MUX to "R Divider/2", you should see a 4MHz square wave clock from the LD output pin. If you don't see this clock, that means the 40MHz reference clock did not go through the R-counter. Possible reasons are: (1) Input signal did not conform to electrical spec requirement. e.g. signal swing, coupling method (2) cold soldering (3) the device is damage (I don't have the data of OSCin bias voltage, but 2.36V seems ok).

Set PLL_MUX to "N Divider/2", you should see a 4MHz square wave clock from the LD output pin (assuming the device is locked). If it is unlocked, you should see clock with a reasonable freq between VCO range divided by 2*N-counter value.

Hi Noel,

OSCin is AC-couple, and checked LDObyp capacitors.

When i set  PLL_MUX to "R Divider/2", on the LD pin i see 3.99997 MHz.

But,  when i set  PLL_MUX to "N Divider/2", i see 3.3V  on the LD pin.