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LMK00101 Single Ended Input

1886332
Expert 1325 points
Other Parts Discussed in Thread: LMK00101

Hi,

From the datasheet I see that:"If the DC coupled input swing has a common mode level near the devices internal bias of 1.4 V, then only a 0.1 μF bypass cap is required on CLKinX*. Otherwise, if the input swing is not optimally centered near the internal bias voltage (of 1.4), then CLKinX* should be externally biased to the midpoint voltage of the input swing"

My OCXO is:"The CMOS output swings from rail to rail – the average DC level is 1.65V for 3.3V supply"

Is this Voltage is "near the devices internal bias of 1.4 V"?

What is the Recommendations for this issue?

Thanks

  • 0
    Expert 1325 points

    can someone please advice?

  • 0
    TI__Mastermind 32575 points

    I would assume your OCXO's LVCMOS output swing is sufficiently fast at 1.4V level.  If this is true, then you can use Figure 12 input circuit (DC coupled input without external resistors for common mode biasing).

    Regards,
    Alan

  • 0 in reply to 1886332
    TI__Mastermind 32575 points

    I confirmed with the IC designer that LMK00101/5 cannot support rail-to-rail input swing from 3.3V LVCMOS drivers. 

    The reason is that a large single-ended input swing overdrives the input buffer stage and causes the input NPN to saturate, resulting in the glitch.

    CLKin can support single-ended swing up to 2 Vpp when CLKin* is biased to midrail.

    To avoid the glitch, parallel (load) termination is needed at the input to attenuate the LVCMOS swing in half. 

     Figure 12 application circuit in the LMK00101 datasheet needs to be modified by adding two 100-ohm resistors (pullup to VCC and pulldown to GND) to support DC-coupled LVCMOS drivers with 50-ohm source termination. 

    For slower or weaker LVCMOS drivers, the 100-ohm parallel terminationresistors may be increased to reduce the loading.

    regards,

    Alan