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LMK01801 LVCMOS CLKOUTPUT CLARIFICATION

Other Parts Discussed in Thread: LMK01801

Hi,

Recently we have tested the LMK01801 Non-PLL buffer, the following observation was found:

Clk out group:CG-2(CLK OUT:4) was programed to out the LVCMOS, but it provides 2.85V DC output instead of clock, this problem exist for all type of inputs & different frequency. At the same time CLK OUT:0 to 3 is working properly(LVDS mode is used). What will be the reason behind this ?

Pin settings of LMK01801 for your reference:

CLK in: 10MHz from OCXO

PIN control: LOW

CLKoutTYPE_0: LOW

CLKoutTYPE_1: Floating(the voltage measured at this pin is 1.55V)

CLKoutTYPE_2: floating

CLKoutDIV_0: low

CLKoutDIV_1: low

CLKoutDIV_2: float

regards,

Rajesh

  • Hello Rajesh, I'll take a look into your problem.  Can you advise me, is this being performed on an evaluation board or a board you have made?

    73,

    Timothy

  • Any update on this - is this test being performed on an eval board, your a board you have made?

    73,

    Timothy

  • Hi Timothy,

    Sorry for the delay in my reply. I dont have the evalution board, I had tried this in my module.

    Regards,

    Rajesh

  • Hi,

    Is there any update on the above query. I am waiting for the reply.

    Regards,

    Rajesh

  • Hello Rajesh,

    Yes - I was able to look into this tonight.  It is strange that you are seeing only 2.85 V DC, is it possible for you to send your schematics of the LMK01801 in a private message to me?

    If you set EN_PIN_CTRL = High, are you able to get LVCMOS output by the table?  Or try a different output -- LVPECL?  (LVPECL would require emitter resistors to ground).

    Try changing CLKoutTYPE_0 to float also with EN_PIN_CTRL = Low.

    73,

    Timothy

  • Hi,

    Thanks for the reply. Kindly find my schematics in the attachment.

    I was not tried with EN_PIN_CTRL = High,, I will try later. But I had changed the CLOUT_TYPE1 from float to LOW the same 2.5V DC is exist.

    6888.lmk01800 switch.pdf

  • Hello,

    Upon reviewing the schematic, I'm a bit confused since there seems to be a contradiction with your prior email.

    CLKoutTYPE_0 is high; this results in LVPECL outputs which could result in just the DC value if no emitter resistor is connected.

    My recommendation for LVPECL (or LVDS) on CLKout2 and LVCMOS on CLKout4 is...

    EN_PIN_CTRL = High

    CLKoutTYPE_0 = High (LVPECL on CLKout0 to 3)     ;   Low (if you want LVDS as per prior message for CLKout0 to 3)

    CLKoutTYPE_1 = Float (LVCMOS on CLKout4 to 7

    73,

    Timothy

  • Hi,

    Nice to hear from you! As I mentioned early I had mounted the EN_PIN_CTRL = Low  & CLK_OUT_TYPE_0:LOW((but in schematics it shows as high)) & CLK OUT TYPE_1:float, why the DC output at the clk out:4 ? What could be the reason behind this ?

    I cann't able to try your suggestion because:

    CLKoutTYPE_0 = High (LVPECL on CLKout0 to 3)     ; 

    CLKoutTYPE_1 = Float (LVCMOS on CLKout4 to 7

    Because it will provide LVPECL output on (LVPECL on CLKout0 to 3) but My termination resisters at the receiving end will supoort only LVDS termination. If i kept CLKoutTYPE_0 : LOW i will get LVDS in all 8 channels, I need LVCMOS output on channel:4 & LVDS on Channel:0-3

    Regards,

    Rajesh.S