I am using the CDCE72010 to generate a 491.52 MHz output using a very low noise ovenized 10 MHz reference and am concerned with phase noise in the 1 to 10 Hz range. I verified that the closed-loop bandwidth is 100 Hz, but I'm disappointed with the close-in phase performance that I measure. It is about -37 dBc/Hz at 3 Hz offset. Ideally I would expect it be 39 dB lower. Since I need to divide the 10 MHz reference by 125 to produce the 80 KHz phase detector frequency, I expect that I might be reaching a noise floor that prevents me from realizing the 20*LOG(M) phase noise improvement. At these low offsets, I am convinced that the VCSO noise is adequately suppressed by the loop, so I am concentrating on the reference input side of the part. I have experimented with different input biasing schemes and nothing seems to change the result. I have also disabled hysteresis.
Any help would be greatly appreciated.