LMK048XX/049XX clock for RF DAC

Thank you very much Noel. This is clearer for me. Of course we plan to drive the FPGA with submultiples of the DAC frequency. Normally it will be the DAC itself who provide the clock to request for data, still we will need a system clock that will be normally 1/4 of the main clock frequency. The reference frequency will also be used for the lower speed processing blocks and as the main system phase reference.

So, If i understand well, for 2.31GHz we have the LMK04805 as only chance. In this case we will ask the chip an LVPECL 2Vpp output for the DAC (I expect this output to be reduced in amplitude so we will pass it through a higher output level high speed comparator), an LVPECL 1.155GHz output and possible additional LVCMOS 70 MHz and 10 MHz outputs for test (preferrable switchable to save power) and LVPECL 577.5MHz and LVCMOS 70 MHz outputs to clock the FPGA.

The reference inputs are 1, 2 or 3 10 MHz redundant signals coming from different sources.

In case we need finally to move to 2.38GHz all is the same except the exact frequencies and the chip must be either LMK04806 or LMK04906, but the second is cheaper and our needs are covered with 6 outputs..

There is another subtle difference which could affect: if the frequency is 2.38GHz (and we use the LMK04906 or LMK04806) the PLL1 multiplies the 70 MHz reference by 34 which is even and allow to double the reference to optimize the final jitter (so following the data sheet the best is doubler ON, R=1, fcomp=140MHz). But in the block diagram the VCO branch divider chain includes 3 dividers ("VCO divider", "N2 prescaler" and "N2 divider") and and two of them has a minimum value is 2 (maybe to guarantee 50% duty cycle?). But even if the "VCO divider" looks like bypassable, that solution looks not possible since we would need Ntot=17 which is not allowed, and we need to change to doubler ON, R=2, fcomp=70 MHz. For 2.31GHz (using LMK04805) fcomp can't be 140 MHz so the best should be doubler ON, R=2, fcomp=70MHz, 2310=33x70, that I think is possible with VCO divider bypassed, N2P=3 and N2D=11. I am checking with the design program and it looks like that but can you confirm I have understood well, if there are differences between the 3 chips at these respects, what is the utility of the bypassable "VCO divider".

Thanks again

Jaime

Thanks Noel, and more thanks for your fast replies. Still I miss two data i asked before, with them my info will be really complete, 1) can you give me an estimation of the total 04805/04806/04906 jitter at 2.3-2.4GHz? because only data at around 200MHz is in the data sheet. I ran quickly the Clock Design Tool (for now in auto mode with all the parameters by default, and without frequency doubler because i don't see it in the program, so R=1 also, which is the combination that the data sheet advices against) and it gives me about 700fs for 1Hz to 10MHz and 164fs for 1KHz to 20MHz, being the latter specified 123fs in the data sheet header (I guess only at lower frequencies even if the PLL jitter is constant with frequency). I wonder the program does not include nonidealities of the output LVPECL buffers when the frequency is high/higher than 1.536GHz. When I ask the program what is the total jitter of the divided outputs the result is the same. This is only true matematically, but I wonder not physically. I will do the exercise of input manually all our parameters, but it is important for me to know if this program estimation is realitic at these frequencies as our jitter goal is 150-200fs (1KHz to 20MHz) because this is what we have achieved with ultra high end low noise synthesizers; as these devices force the need of an external 1st PLL and an aditional output divider/distributor chip, we are tempted by the high density of the TI parts. I guess if we could get better jitter using a combination of one of those devices (like ADI AD951X, Hittte HMC83X or RFMD similar parts) plus divider/distributors as LMK01801 which is reported 50fs at 800MHz. As the LMK01801 LVPECL specification minimum max freq is much higher perhaps contribute less additional jitter to a 2.3GHz output...

2) The program does not allow to use the frequency doubler? I don't find it

Thanks again...

Jaime

Hi Martin,

1) I don't know whether the tools has consider nonlinearity for output freq > 1.5GHz. But the tool is by far the most accurate simulation tool I have ever seen. I don't have 70MHz VCXO, I will take some data with a 61.44MHz VCXO in next week, as I am traveling now.

2)Yes, the tool does not support doubler.

Hi Noel,

Excuse me, I am sure not, but in LMK04906 data sheet page 84, "freq planning"... it says that output divide values are 2 to 1045. According to the main BDG, clock design SW functionning and the register descriptions themselves the range of the output dividers is 1 to 1045, otherwise 2GHz outputs would not be possible Can you confirm me that it is a simple errata or maybe the paragraph is speaking of a different thing?

Thank you very much.

Jaime

Hi Jaime,

The divider values are 1 to 1045, so when both VCO and clock divider are equal to 1, you could obtain 2GHz output.

On page 84, I believe this is not typo but when we say "divide", it normally means divide by 2 or more.

Thanks Noel,

tell me it is common to use several inependent regulators to fed digital, analog, or different supply blocks of complex ICs, even when the power supply voltage is the same value for all or some of them.

In the 04906 App info and ev board, uit is recommended instead to use a single regulator but needing a complex and delicate ferrite filter tree (some ferrites not convenient, some other yes...)

Would it not be an advantage to use multiple output regulators or multiple regulators to decouple also the low frequency from supply to supply instead trust all in the ferrite filters and decoupling? independent regulators+ independent decoupling/filtering results in better isolation at low freq (maybe the same at high freq). Any recomendation or it is better to follow the guidelines the application schematic at this respect?

We have used with success regulators for extreme low dropout and low noise as TI TPS796XX or Linear LT196X or the multiple output regulators as the ones available from Hittite with which you can save circuitry. But for that we would need data of current consumption of each independent supply that are not in the data sheet.

Thanks in advance, again.

Jaime

Hi Jaime,

I think one of the concerns of recommending multiple LDOs is the system cost is getting higher, which I believe most of the customers are not willing to see. Another concern is this would require more pcb space to fit several LDOs.

Performance wise, it is definitely good to have multiple LDOs providing supply to the device, this would increase the isolation between different Vcc pins.

The ferrite bean approach was obtained from empirical result and is a proven low cost solution, that's why we recommend it in the datasheet.

Thanks Noel, for the purpose of using multiple regulators or a multiple output regulator as i commented, I would need data of the power consumption maximums of the independent branches, not to reduplicate large regulators. My multiple regulator can deliver up to 200mA each branch but all I know from LMK04906 is the total power consumption between 350 and 470mA depending on the processes being performed. I would need VCO, CP1, CP2, etc. independent supply current needs

hi Jaime,

Just did a quick measurement on a LMK04816 EVK with Clock Group 0, 1 and 5 are LVPECL, Clock Group 2, 3 and 4 are LVDS. OSCout is LVPECL. Typical current on each Vcc pin is as follows:

Thank you Noel, but can I asume that my LMK04906 will have the same current consumption for each pin?

Hi Jaime,

Yes, expect for Vcc2, Vcc3, Vcc10, Vcc11, Vcc12 and Vcc13 because LMK04906 has less clock output driver.

Hi Noel, we progress with the aplication design. I am now in front of the primary reference circuit design and I wonder if TI can help to decide the interface. Even if it is the lowest frequency part, we consider it critical because in our phase noise budget, given the low noise of the internal VCO, the CLK IN phase noise is the predominant component by far.

We have a 10 MHz or 20 MHz CMOS OCXO that should be usable directly and unipolarly to a first LMK04906 CLKIN input. But we have to attend a second input that is sinusoidal and thus we thought in using a comparator at least for this input, and drive a second redundant CLK IN.

We used a 3ns CMOS comparator as reference clock interface and flange cleaner in the past for this kind of application (unipolar output) but now, as far as the total jitter goal is so low and these comparators don't speciffy additive jitter we have prepared another better comparator, differential I/O, with PECL output that can drive directy the LMK04906 CLK IN, in this case bipolary.This comparator specifies 500ps prop time and opposite to the former does specify additive jitter, even if only the random part (1ps). By comparison with other comparators we can guess that the total jitter including deterministic is about 10 times greater, 10ps. Tis is very far and worst than the 2.4GHz output goal but of course of all this jitter only the narrow PLL1 bandwidth will accept a fraction and if you make the account considering flat (but it is not... we can't measure it), it is aceptable.

My two basic questions, are: 1) do you think is necesary to use the PECL comparator for the 10 MHz sinusoidal reference? because there is a large penalty in power consumption when using the PECL comparator. WIll it give better result that the CMOS comparator, or the direct sinusoidal input? and the second and more important, 2) should we use also a comparator for the CMOS OCXO input, even if it is not needed for compatibility? This is a very high end estability and phase noise oscillator, but rise/fall maybe use slow logic and specifies 10ns 10to 90% LV3.3V output, as the LMK04901 specifies a min of 0.15 to 0.5 V/ns slew rate so it is not good in excess in this. On the otehr hand we have tested the breadboard with sinusoidal input and the result was good. Given your acknowledge of the CLK IN LMK04XXX internal CLK IN receiver, can you / TUI/ NS recommend us if does it worth to insert a comparator at all, and if is recomendded , does it worth to put a very fast and low jitter one?

Thanks in advance

Jaime

Hi Jaime,

No translation is required for OCXO, it is already good enough to drive LMK.

I think CMOS compartor is also good enough and is required to translate sinewave to squarewave. the slew rate of a 10MHz sinewave is too slow. If the signal swing is not high enough, sometimes LMK may not lock. The additive jitter should not be a big deal as you have VCXO in PLL1 to clean it.

Noel, in this time we have changed our plans. We have now a frequency (around 2340 MHz) that needs the use, again, of LKM04805. But my main question is independent, I think, of that.

Is it possible to use the LMK04805 in this "special" configuration,as a part of a 3PLL system?:

- Use PLL1 to lock a VCXO (input fin, I believe) to the reference that inputs in CLKIN0

- The VCXO fin signal does not have to be routed to the PLL2 reference input OSCIN. We want to insert another device in the middle that will generate a new reference from the locked VCXO signal. It is this new frequency in the order of 150MHz that will be used as PLL2 OSC IN to lock the internal VCO to it.

Using the large complete diagram I can see that the connections are possible (for example, the VCXO will arrive to the N divider via FIn input), but some explanations make me doubt as far as fin can be used also to feedback to PLL2.

I think it can be done nevertheless, can you confirm?

- Signal 1 (OCXO reference input) to PLL1 R via CLKIN0

- Signal 2 (VCXO output) to PLL1 N via FIN, FIN is not to be feedbacked to anywhere, only be used to enter to the OSC or VCO PLL1 input.

- Signal 3 (it is a signal that we need to generate fractionally with an auxiliary synthesizer from the VCXO one) is, let's say, replacing the role of the VCXO signal in PLL2. This signal 3 near 150 MHz has to be used as reference by PLL2 to lock the VCo at around 2340 Mhz (%16 that meets the need to be even).

I think i can do it... but please confirm, as the LMK family connections are not designed with this possibility in mind and I am afraid to discover that there is some "default" connection that makes it impossible to create this architecture. Otherwise I will spend a lo of time with the connections and controls :). Also it is interesting to know if there is a way to use the design SW to simulate phase noise but as far as my auxiliary synthesizer is not included in the simulation, I can always put numbers in PLL1, calculate the locked VCXO noise, take note, run the otehr synthesizer simulation, calculate the new oscillator PN, and come back to the TI program to calculate the PLL2 with this new reference.

Thanks in advance

Jaime Martin

Hi Martin,

Yes, you can use it as two separated PLL. To do this, you have to put the device in "dual PLL, int VCO, 0-delay" mode; enable Feedback MUX; select FBCLKin as the feedback mux input.

In the Clock Design Tool, you have to manually input the phase noise profile of the VCXO and signal 3, the tool will do the simulation for you.

Thanks Noel, very good to be sure of it. Now I am simulating, but the problem is that, as far as the PLL2 reference source is suppossed to be an external VCXO locked to PLL reference, I can't introduce the PLL reference "VCXO" easily. What I did is to build a virtual PLL1 witha very narrow bandwidth, for a virtual VCXO can easily assume the noise of the external fractiona synthesizer that I computed with another source's program, and iterate until the "VCXO" gets exactly the noise of that external synthesizer. the resuls don't seem crazy, just a bit worst than in my simpler previous design.

Can you clarify me what do you mean with "signal 3"?

Thanks

Jaime Martin

Yes Noel. This is exact :), you got it perfectly. In fact I am doing exactly what you propose; the only drawback is that when I come from the external synthsizer with the signal 3 noise, I can't input it directly anywhere as far as the LMK tool is waiting for reference  and VCXO independently, to compute the PLL2 reference input from the PLL1 output. What I do is to create a false PLL1 with a very narrow bandwidth (to minimize the PLL1 reference noise effect) and give the VCXO the noise of the external synthesizer; then trimming a little bit until the PLL1 output phase noise is exactly the same as the one i got in the external synth. I guess if there is a way to configure the dual PLL in the beginning to accept the data in a more direct way, but I have not found it. I am using the 1.34 version of the tool and maybe there are new revisions that allow more possibilities?

The result is just as good as expected, a limited impact of the external synthesizer VCO adds basically a noise which is relatively similar to the internal LMK synth VCO noise (a ultralow noise VCO locked to the VCXO) : the overall result is so in the order of 3 dB degradation, because the PLL2 now does not see a crystal but a wideband noise VCO.

Than you very much.

Jaime

Hi again. I am now changing from the 04906 to the 04805. I think i don't have to worry of the fact that the output frequency spec for th former is 2.6GHz while the one for the latter is 1.536Ghz, as far as the outputs are really exactly the same type and the 1.536 Ghz spec is the LVPECL spec that affects only the output swing and that can overrided using the 2VPECL format. Anyway I have already measured the LMK04906 output up to 2.4Ghz and would like just to be sure that the LMK04805 outputs are exactly the same electric / frequency range specification.

Best

JM

Hi Martin,

Right, both devices have the same electrical behaviour except for the VCO freq.