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Low frequency PFD feedback

Matthew Beals
Prodigy 50 points

I need to take a reference clock as an input and output an identical version delayed by some programmable time.  The input clock can have a maximum frequency of 4 kHz and realistically be as low as 10s to 100s of Hz.  The pulse width of the clock is also fixed at 10 us.

My intended approach is to sample the input clock with an MCU and replicate the frequency via PWM, then feed both signals into a PFD and use the feedback to fine tune the phase lag (forming a digital PLL).

Most of the PLL IC's I see in the catalog seem to be designed for the MHz range.  Is there an IC that would be well suited for this application and operate well in this frequency regime?

  • 0
    TI__Mastermind 32575 points

    As you discovered, our portfolio is largely comprised of analog PLLs, whereas your application seems to need a Digital PLL to handle low PFD frequencies in 10~1000 Hz range.

    What is the end application for the desired digital PLL device?  

    Where are the input clocks coming from and what do the output clocks drive in the system?

    Does it have to be a single chip solution?  

    What is the required jitter performance?  

    Do you require reference switchover or holdover on loss of reference?

    Regards,

    Alan

  • 0 in reply to Alan O
    Prodigy 50 points

    Hi Alan, 

    Thanks for getting back to me.  I'll answer the questions inline:

    What is the end application for the desired digital PLL device?  

    I am building a controller for an actively Q-switched diode laser.  The laser needs to be synced to a TTL output by high speed cameras, and I need the phase delay to adjust for trigger and line latency.

    Where are the input clocks coming from and what do the output clocks drive in the system?

    The input clock will be from either an external signal generator or from the output of a camera.  It is being passed through an isolated logic buffer such that the signal will be a 5V TTL.  The output clock drives a 5V digital logic level input built into the laser diode assembly.

    Does it have to be a single chip solution?  

    It does not have to be a single chip solution.

    What is the required jitter performance?  

    I would like to keep jitter ~10ns or less, but can likely tolerate more.

    Do you require reference switchover or holdover on loss of reference?

    I don't suspect I need either.  Signals should be clean enough that I'm not worried about losing lock due to noise.  In the event that the clock speed is changed, I would like it immediately break and then resume once locked again. 

    My design for the rest of the system is using a MSP430 5 series chip with the timerD peripheral and high resolution mode.  I have the input (reference) clock tied to a CCR and dual PWM outputs (so that I can generate dual, phase shifted clocks) so that if needed I can allow the controller to act as the master for the laser and the cameras.  

    Would this work for a digital PLL?....possibly using a CCR on the reference clock to sync it with the output?  I did consider adding a J-K flip flop (comparing the input reference clock a PWM generated clock going to the laser) and feeding the output back to the MCU.