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CLOCK GENERATOR

eli
Guru 13485 points
Other Parts Discussed in Thread: CDCM6208, CDCM61004, LMK03806, CDCLVP1204, LMK00304, CDCM61001

Looking for clock  generator that can produce 8 LVPECL outputs of 125M each, low jitter. Prefered for input of 19.2 (CDCM6208?)

additional Similar solution for 4-6outpts (CDCM61004?)

  • 0
    TI__Mastermind 20900 points

    Hello Eli,

    8 LVPECL outputs can be generated with LMK03806.

    the 4 output version could be done with CDCM61004 if a 25MHz Xtal is used.

    3rd option could be CDCM61001 with 25MHz xtal plus buffer (LMK00304/6/8 or CDCLVP1204/08).

    Best regards,

    Julian

  • 0 in reply to Julian Hagedorn
    Guru 13485 points

    Hello Julian,

    Thanks!!

    Please confirm that LMK3806 can be used from external  external 

  • 0 in reply to eli
    TI__Mastermind 20900 points

    Eli,

    sure, the LMK03806 is an RTM'd device and it's free to be used by anyone.

    Best regards,

    Julian

  • 0 in reply to eli
    TI__Mastermind 32575 points

    Hi Eli,

    Can the 125 MHz outputs be generated from another input such as 25 MHz external clock or crystal, or must they be synchronized to a 19.2 MHz external clock in the system?

    Also, can the output clocks be AC coupled?

    I'd like to point out that CDCM6208-V1 supports Pin Mode option (#8) to generate 8x 125 MHz outputs (4x LVPECL-like + 4x HCSL) using a 25 MHz input (external clock or crystal).

    Regards,
    Alan

  • 0 in reply to Alan O
    Guru 13485 points

    Hi,

    Can the LMK03806 get 19.2Mhz LVCMOS from LMK04820 ?

     

    The  CDCM61004 clearly says it can without crystal.

     

    The point is to generate the 125Mhz from reference 19.2M clock that was jitter cleaned.

     need for that fractional PLL- Do we have like this?

     

    Yes can be AC coupled .  

     

    The CDCM6208-V1 can not support 8x LVPECL , and it's ~150fs jitter  is about like the LMK03806

    B.regards

    Eli

  • 0 in reply to eli
    TI__Mastermind 32575 points

    LMK03806 can generate up to 12 LVPECL outputs with ~350 fs RMS (10 kHz to 20 MHz) from a 19.2 MHz input.  Because 19.2 MHz is not nicely related to the VCO frequency (2500 MHz) needed to generate 125 MHz output clocks, the PLL PDF can only operate at 800 kHz, which causes higher noise contribution from the PLL and thus higher RMS jitter. 

    Does this meet your jitter performance spec?

    Regards,
    Alan