Hi,
I am using CDCE913 to generate three output clocks, Y1 Y2 Y3. Because of design constraints the, i cannot use any of the clock signals as an interrupt to synchronize my design, hence using internal DSP(C674x) timer. My question is can we setup the outputs Y1 2 Y3 in tri-state mode and provide the clock into the CDCE, and provide enough time for the clock signals to stabilize(internally), and then if i enable these three outputs what is the possible jitter or stabilization time? not much clear in the data sheet.
