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LMK048** Detailed performance

jacky lu
Intellectual 340 points
Other Parts Discussed in Thread: CLOCKDESIGNTOOL, LMK04816

Sir:

    I need  do a design of time-interleaved ADCs of 14bit, so the time tree must be in high performance. The new generation low noise PLL of LMK048** and LMK049** attract my attention. After read the datasheet of these devices, I still have some doubts about the feature and the application.

(1) the datasheet give the jitter performance is about 100fs for LMK048**.  Is it the parameter of JITTERadd? 

(2) LMK048** can be used in dual PLL mode and single PLL mode, which mode has better performance? In which mode was the device tested to get the jitter performance of 100fs.

(3) If I want to use the device in dual pll mode, how do I construct the external loop filter?

Jacky

thx

  • 0
    TI__Mastermind 28590 points

    Hello Jacky,

    jacky lu said:
    (1) the datasheet give the jitter performance is about 100fs for LMK048**.  Is it the parameter of JITTERadd? 

    No, this is total jitter.  The narrow loop bandwidth of PLL1 attenuates input jitter.  Also, keep in mind that RMS jitter is dependent on integration bandwidth.

    jacky lu said:
    (2) LMK048** can be used in dual PLL mode and single PLL mode, which mode has better performance? In which mode was the device tested to get the jitter performance of 100fs.

    Both have the ability to achieve the same level of performance.  However dual loop allows a noisy input reference clock to be cleaned by a narrow loop bandwidth PLL1 using a VCXO or Crystal to provide a clean reference to PLL2.  If you have a clean reference, as is often the case for clock generation - then you do not need to use dual loop.

    jacky lu said:
    (3) If I want to use the device in dual pll mode, how do I construct the external loop filter?

    Please use the ClockDesignTool to assist in loop filter design and simulation, note there are also some training videos on the ClockDesignTool website.  For dual PLL, loop filter 1 should normally be narrow - for example 10 to 200 Hz.  If the ClockDesignTool does not have a noisey phase noise plot loaded as a CLKin reference, sometimes it will design wider loop bandwidths, like 1 to 3 kHz.  In this case, you can enter the loop filter design window, type in a lower loop bandwidth, like 100 Hz, then re-calculate the loop filter.

    In addition to the ClockDesignTool, please see the Choosing Loop Bandwidths for PLLs slides in the Clocks E2E files section.  Here is a link:

    http://e2e.ti.com/support/clocks/m/videos__files/664163.aspx

    Please note slide 17 which illustrates how the same PLL can have better or worse performance depending on the phase detector frequency.  Designing your PLL, or second PLL in a dual PLL system to have high phase detector frequency is important in achieving lowest possible jitter.  For best possible performance, it is also important that your reference (or VCXO in dual loop system) have phase noise which doesn't impact PLL performance (below loop bandwidth).

    73,

    Timothy

  • 0 in reply to Timothy T
    Intellectual 340 points

    Timothy:

         Thanks for your reply and kindness! Because some reason in my lab, I can know consider this question again.

    In page13 of datasheet LMK04816, the doc give two JITTER test meathod. One is "CLKout Closed Loop Jitter Specifications usinga Commercial Quality VCXO", the other is  "CLKout Closed Loop Jitter Specifications using the Integrated Low Noise Crystal Oscillator Circuit".

    (1)Dose the first means the LMK04816 works in dual PLL mode, and the second means the device works in single PLL mode?

    (2)For the first test method, note16 indicate the VCXO used is CVHD-950-122.880, but the datasheet do not say which crystal it used. I mean the crystal that supply clock signal to CLKinX port.

    (3)For the second test method,  Crystal used is a  Vectron VXB1-1150-20M480 and Skyworks varactor diode SMV-1249-074LF. Is there a schematic that show the connection?

    (4) In your reply, you said the 100fs is the total jitter. What do you mean by the word "total jitter"? Is it the jitter including the jitter of reference clock, jitter of external VCXO and jitter of  internal integrated VCO? Is it the total jitter of the output clock when LMK04816 works in dual PLL mode?

    Thank you!

    Best wishes

    Jacky