Hi,
I use CDCLVC1104PW to buffer a 2.5V 125MHz CLK
Trace length on the outputs is around 13cm (5000mil)
2 things surprised me
a) I hardly reach 2.0V on the clock waveform.
b) lots of reflections
See yellow waveform below (I used a 5GHz differential probe, very short connections)
I used 0R series termination as per datasheet recommendation. As you can see from the plot, that doesn't seem right ?
When running IBIS sims, I see however a tremendous variation in reflection over slow/typ/fast, so I'm not even sure I can really rely on a particular series termination ?
In none of the IBIS simulations, I see a sign of reduced output swing. Any idea why ?
I currently added a 470R pullup to 2.5V to help increase the high level at the expense of a worse low level, but I don't find it a very clean solution.
Rudi