Hi all,
I am using 2 CDCE62005 IC to get 10 outputs. These outputs I am using for clocking ADCs and DACs on my board. I am using under sampling to get 256/335 of 88 MHz.
These ADCs and DACs are used in phase and amplitude stabilization of a sinusoidal signal. When I program both initially it starts working, but after a shutdown the clock output shows strange noise that sometimes after reprogramming gets removed. As this card is to be delivered to a laboratory, this strange behavior is unexpected. The spectrum of the output clock sometime shows a varying spectrum of 9-11KHz. and the phase changes dramatically between 10 to degrees, but after reprogramming the phase variation remains of the order of 0.1 degrees.
I tried to change the power supply from initial to a better one presuming the backplane noise is entering the loop, but the situation remains same. When I program CDCEs initially output shows no noise, but after a shutdown of 1 hour, the noise starts coming again as soon as I program my FPGA.
I am not able to find the reason for this.
PLZ explain me what is wrong. I set the loop bandwidth using latest CDCE GUI it shows no warning and a very good phase margin of 55 degrees with a bandwidth 120KHz. with a spur of 41 db down. My charge pump setting is 1.25mA. Kindly tell me what is the problem if the clock output is jittery and in what way the synchronization takes place.
Kindly also tell me how can CDCE VCO be manually calibrated.
Thanks in advance.
Regards.