Hello all,
I'm working on a project which is using a Divide by N component, CD4059A. In fact, I have a problem with it.
I'm trying to configure it in order to have N=1000. So, I fixed input J1 (pin 3) and J13 (pin 10) at "1" logic. J2,J3,J4,J16, J15, J14, J13 are fixed to "0" logic (pin 4 to 9) as J5, J6, J7, J8, J9, J10, J11, J12 (pin 15 to 22)
L (Latch Enable, pin 2) is at "0" logic as kc (pin 11). Ka and kb (pin 13 and 14) are at "1" logic.
Vss (pin 12) is 0V (same value for inputs which are at "0" logic) and Vdd (pin 24) is 12V (same value for inputs which are at "1" logic).
My input signal is a square wave signal 12V peak to peak voltage, average voltage 6V 16.5 kHz but my output signal is 0V.
So, I would like to know if someone can identify my problem and give me a solution, please ?
Thank you in advance,
Simon Michaut,