Hi,
I was thinking about to use CDCVF855PW to generate two SSTL-2 clock for a JEDEC 266 DDR.
I start by saying that I've never used before a SSTL-2 buffer and that I'm not so much expert in differential standards.
I'd want to know more about the input stage of CDCV855PW (CLK,CLK# ): is the input stage of CDCVF855 internally ac coupled as in the CDCV850 it is?
I want to connect a LVDS/LVCMOS configurable output stage of my PLL to the input stage of the CDCVF855. (For CDCV850 (another TI device with SSTL-2 outputs) there is the "scaa058.pdf" application note, where I can read that CDCV850 has ac internally coupled inputs and describing how I should drawing the electrical interface both for a LVDS or a LVCMOS driving circuit.
Could anyone suggest me how I should interface a LVCMOS/LVDS chipset to CDCVF855?
Thank you in advance
yours sincerely
ELENA