• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 21 subscribers
  • Views 396 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

trouble getting desired frequency on LMK04806b

Tim P
Prodigy 40 points
Other Parts Discussed in Thread: CLOCKDESIGNTOOL

Hi,

We're having trouble getting the desired frequency on our LMK04806B device.

We have 100 MHz VCO for PLL1 (i.e. OSCin is 100 MHz). 

We set the PLL2 R & N to 200 & 2500 which should give us an internal VCO of 2500 MHz.

We set the clock divider to 100 which should give us 25 MHz on the output but we're seeing 25.2 MHz.

If we follow the recommended programming we get 24.8 MHz.

Any thoughts about what registers we're not programming correctly or in the correct order would be greatly appreciated.

  • 0
    TI__Mastermind 28560 points

    Hello Tim,

    Hopefully the info below can help you to troubleshoot your problem.

    I presume the PLL2 digital lock detect reports unlocked?

    To debug such a problem, I recommend using the PLL2_R/2 and PLL2_N/2 outputs on LD and HOLDOVER status pins.  Program LD_MUX and HOLDOVER_MUX as required.  Probe these outputs to see if the feedback or reference path is providing an unexpected output.  If in lock, then both output should be at the exact same frequency, half the phase detector frequency.

    I'm surprised your running PLL2 phase detector frequency at such a low rate, 1 MHz.  For best PLL2 performance, I recommend running at maximum phase detector frequency.  See http://e2e.ti.com/support/clocks/m/videos__files/664163.aspx for more info on loop bandwidth choice.  See slide 17 in particular.  Also see the ClockDesignTool for loop filter design.

    Is this issue on the evaluation board?  Did you update the PLL2 loop filter?  Is PLL1 locked?  Keep in mind that PLL2_P register is also inline with the PLL2_N register, so you need to account for that in the total N divide.

    I'm not sure what the recommended programming is and how it differs from yours.

    73,

    Timothy

  • 0 in reply to Timothy T
    Prodigy 40 points

    For closure and anyone else who may search and find this thread helpful...

    Our problem turned out to be the PLL2 charge pump 2 current and polarity. 
    After setting the current to the maximum and the polarity to negative, we were able to get accurate frequency settings.

    We have been using the ClockDesignTool to help set the values for the LMK04806B.

    The reason for the low phase detector frequency rate is for the clock granularity. 

    It seems that the more granularity we want the lower the phase detector frequency will be.

    The recommended programming procedure is described in the datasheet.  Basically it is R0-R31.
    This didn't seem to make much difference.