• State
  • Locked Locked
  • Replies 6 replies
  • Subscribers 22 subscribers
  • Views 766 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

search for a high performance clock cleaner

jacky lu
Intellectual 340 points

Other Parts Discussed in Thread: LMK04906, CLOCKDESIGNTOOL, LMK02002

sir:
   

    My clock generator produce 4 channel clocks with the frequency  250M~400MHz, and each channel pass through a VCDL(voltage control delay line). But when the clock pass through the VCDL, the phase noise increase, with the RMS jitter about 400fs(12KHz~20MHz). I search for a simple jitter cleaner, which can filter the phase noise of each clock. I hope  the jitter cleaner can produce a clock with RMS jitter below 100fs.

Is there some device that meet my requirement?

Thank you!

Jacky

2013-06-05

  • 0
    TI__Mastermind 32575 points

    You might consider LMK04906 which is a dual-loop jitter cleaner/clock generator with 6 DIFF outputs and capable of 100 fs rms jitter. 

    You can try to download/install CLOCKDESIGNTOOL to assist with device selection (LMK/LMX family of PLL devices), frequency planning, PLL loop filter design, and phase noise/rms jitter simulations. 

    Regards,

    Alan

  • 0 in reply to Alan O
    Intellectual 340 points

    Alan:

          Thank you for your reply!

          I　know LMK048** and LMK 049** are dual-loop clock generator in high performance and can produce output clock with 100fs. But these devices are complicated to configure. I need a simple jitter cleaner for which I think a single pll is sufficient.

        What about LMK02002? I know this device is a single pll and is good in phase noise, but how can I estimate the total phase noise  when adding the external VCXO? Besides, is LMK02***  capable of keep the output and input in 0-delay mode?

    Thank you

    Jacky

  • 0 in reply to jacky lu
    TI__Mastermind 32575 points

    For LMK02002, you can use CLOCKDESIGNTOOL and use "Enter Custom Phase Noise" to import the phase noise of your VCXO and simulate the output phase noise, which will include noise contribution from the PLL, loop filter, and clock buffers.

    LMK02002 does not support 0-delay mode.

    Regards,
    Alan 

  • 0 in reply to Alan O
    Intellectual 340 points

    Alan:

          Is there a simple clock jitter cleaner like LMK02002 that support 0-delay mode?

    Thank you!

    Jacky

    2013-06-13

  • 0 in reply to jacky lu
    TI__Mastermind 32575 points

    What is your input clock frequency?  Will your output clock frequency be equal to your VCXO frequency?

    Regards,

    Alan

  • 0 in reply to Alan O
    Intellectual 340 points

    Alan:

          The input clock frequency is 250MHz. It is hard to find a VCXO exactly equal to the same frequency. So a VCXO with higher frequency is more probable.

    Thank you!

    Regards

    Jacky

    2013-06-14