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CDCE937 Power-up sequence and Yn output

Toshio Ushikubo
Mastermind 9620 points
Other Parts Discussed in Thread: CDCE937

Hello,

Please answer my customer's problem.

Power up sequence of customer's board is VDDOUT(3.3V)  ON first and VDD(1.8V) ON next.

EEPROM is Factory Default Settings as explained in Table 4. of datasheet and S0 is set LOW, so customer expects Yn output are Hi-z until S0 is changed to HIGH.

But Yn output High level until VDD(1.8V) is ON (between 3.3V ON and 1.8V ON period).

   Q1: Are their any requirement of power up sequence?

   Q2: Yn must be Hi-z after 3.3V is ON in their system.

          Are their any countermeasure to keep Hi-z after 3.3V is ON?

Regards. 

  • 0
    Mastermind 9620 points

    Hello,

     

    Followings are additional information for my previous post.

    I confirmed that same phenomenon are observed using CDCE949EVM as following waveform.

    4861.TEK00002_for E2E.tif

     

       Q1: Is this phenomenon(Y1 outputs high until Vdd is ON) normal behavior of CDCE937 ?

       Q2: Yn must be Hi-z after 3.3V is ON in their system.

              Are their any countermeasure to keep Hi-z after 3.3V is ON ?

     

    Please anyone answer above question

    Best Regards.