CDCE62002 and Phase Noise Specification - Novice Question

Hello,

Here are my comments in blue

I have been examining the CDCE62002 and have a novice question with regards to the Phase Noise Analysis.

On page 14 of the data sheet, there are 2 (two) tables detailing the phase noise for the IC.

Table 2 indicates the phase noise for the refernce input clock of 30.72MHz. The phase noise entries are from 10kHz to 20MHz, improving as the bandwidth increases.

What exactly are these phase noises refering to - is it the VCO internal to the CDCE62002 ?.

These phase noises refer to output phase noise. This is the combination of the phase noise of the input clock , PLL in- band, VCO and output buffer.

I propose to use the LVCMOS output set to 38.4MHz clock frequency. The phase noise reduces as the phase noise frequency rises from 10kHz to 20MHz. Why is this ?, and what is the significance of these values ?.

In generally VCO is noisier close to carrier frequency (such as 10 kHz) and shows better phase noises at wide band (away from carrier, such as 10 MHz). That's why at higher  offset frequency,  the phase noises value looks better .

Moving to Table 3, the reference is a 25MHz crystal reference. The phase noise for the 25Mhz reference crystal is blank, and for the LVCMOS output the phase noise reduces as the frequency increases from 10kHz to 20MHz. Assume the answer as to why is based on the previous answer to this question.

Yes.

Am i correct in assuming that the phase noise is blank for the crystal input due to the crystal not exhibiting any measurable phase noise ?.

We can measure phase noise of a crystal with a buffer (crystal + oscillator stage). We could add this into the datasheet.

The decreasing output frequency of the LVCMOS clock signals seems to indicate an improving phase noise. Hence is this a correct assumption that using a 38.4MHz crystal for a 24.576MHz clock and a 36.864MHz clock will improve upon the Table 3 LVCMOS values for phase noise ?

It may improve the phase noise at lower output frequencies. But output  buffer may impose its own limit.

The Loop Bandwidth for both tables is set to 400kHz.

Is 400kHz the optimum setting for a 38.4MHz reference crystal providing 2 clock output at 24.576MHz and 36.864MHz ?., or should the lower Loop Bandwidth of 70kHz be used ?.

With clean input (like crystal), higher loop bandwidth provides better performance. With 70 kHz loop bandwidth, you will see worse performance around 100 kHz region. Around 400 kHz loop bandwidth should be the optimum value.

I am not bothered about the time taken to obtain the required output clock frequency, as long as the reduced frequency bandwidth of the loop increases stability of the system, and reduces phase noise.

Higher loop bandwidth is better here.

Thanks,

Firoj