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LMX2541 Startup

Dmitry Vasilenko - Arrow
Expert 1380 points

Other Parts Discussed in Thread: LMX2541, LMX2531

Hi,

my customer designs a clock generation module on LMX2541  pin compatible with the module based on ADF4106. This is done to avoid VCO tuning.
However, the startup  waveforms of the two circuits are different. LMX 2541 requires that signals Data, Clk, LE are to be set to "0" after loading. For ADF4106 buffer is used, that blocks the activity of the common SPI bus with the help of signal LE:

In this circuit, the signal LE is "0" only during synthesizer loading, and the rest of the operation it is in the state "1", thus blocking the activity of the signals CLK and SDI. The loading diagram of ADF4106 uses a lower version of the LE signal behavior:


Since the customer is using the "full chip" mode of LMX2541, the calibration process of internal VCO starts after loading the final register R0. In order not to interfere with this process, the signal LE must not be kept in a state of "1" for more than 1 us (Tewh).


The customer asks to clarify why it’s needed to keep the signals Data, Clk, LE in the state "0" if a normal shift register is used and the counter is updated on rising edge of LE? What happens on the last falling edge of LE at the end of startup process? What happens if I do not lower the LE signal to "0"?

  • 0
    TI__Mastermind 28031 points

    Dmitry,

    If the LE pin is kept high, it will freeze the VCO calibration and cause it to malfunction.  So although the action of LE going low to high starts the calibration, the band switching circuitry will be locked from changing until the LE goes low.  The end result is that the VCO can calibrate to the wrong frequency.  So it's not really the falling edge of LE, but rather when LE is high, only part of the VCO calibration can run.  To answer your question, if you never lower LE to low, the VCO calibration will be locked and the VCO will be stuck in the wrong band.   The 1 us requirement has a lot of margin on it, but if this gets in the 10's of us, then the VCO will only partially calibrate and will go to the wrong frequency.  

    Now for CLK and DATA, I don't think that this is so critical, but this is the way that we have tested and characterized the parts.

     

    Regards,

    Dean

  • 0 in reply to Dean Banerjee
    Expert 1380 points

    Thank you, Dean. I talked to the customer and they have implemented the following way of the calibartion:

    After a final register R0 is configured the signal LE is put to high state for 500 ns, then set to low for 1000 us, which should ensure the calibration of the generator:


    This type of control of LE does not give the desired result: the synthesizer does not start.


    Could you please check and advise.

  • 0
    TI__Mastermind 28031 points

    Dmitry,

    The answer is that it is more than just a shift register.  The LE pin is also tied to our internal readback function when pulled high.  This interfers when the VCO calibration is running and maybe (not sure) with the digital lock detect.

     

    Concerning the LE signal being returned to the low state, this 1 us applies to after the R0 or R1 register is loaded, since the action of programming these registers activates the VCO calibration.  The 1 us is a conservative number and has margin in it.     The VCO calibration works by switching the VCO between the 128 different frequency bands and this is run by a state machine clock.  The action of holding LE high interfers with this circuitry that switches between these frequency bands and the state machine clock such that the device does not switch and it just stays at the same frequency band until the LE is brought back to low.  This is likely related to the fact that holding LE high activates the internal readback function that we use for diagnostic purposes.   Note that if you were to program and keep LE high for less than 1 us, then go low and hold it until the VCO calibration finishes (typically a few 100 us), then this would address this issue.  However, I know on the LMX2531, which is the predecessor to this part, that holding LE high also interferred with the digital lock detect as well.

    As for CLK and DATA, the truth is that it is probably not necessary to keep these lines low.   The reason that we say these things in the datasheet is that this is the way that we characterized the device and the way that we test in production. 

    So in summary, there is probably a way to work around this, but in the datasheet we prefer to recommend one way and test and characterize this way.  Because of the issue programming with LE going high, we just say to bring them all back to low.  Giving multiple options not only confuses customers as to what is the right way to program the device, but also exposes us to more liability to test for.   Although it will probably work keeping CLK and DATA high and holding LE low enough just long enough for the VCO calibration to finish, this is not the datasheet recommended way of programming and NOT GUARANTEED.

    Regards,

    Dean