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Clock Trigger Generator with LMK04828

fearghal rudden
Intellectual 480 points

Other Parts Discussed in Thread: LMK04828

Hi,

I am starting a design and wanted to ask for feedback on the LMK04828 clock jitter cleaner and distributor. The aim is to generate 8 trigger signals from the sysref output clocks (one output will have a fanout buffer to generate the 8th signal). The requirements include:

  • The sync outputs should be able to multplex between: external sync input, onboard 1pps from GPS module, FMC sourced sync
  • The sync should be resynchronised to the generated clock after multiplexing
  • It should be possible to lock the clock to a 1pps pulse.
  • It should be possible to shift each sync with 1/4 clock cycle resolution (ie 90,180,270 )

 

Clkin1 on the device is driven by a clock source that we would like to sync our trigger signals to. Figure 5-2 in the datasheet implies that this is possible. The frequency of clkin1 will be approximately 2.5GHz. Clkin0 will be driven by an external trigger signal  to drive our trigger/sysref outputs. The sync pin will also have inputs from a locally generated 1 pulse per second signal or a sync signal sent from an external FPGA. From what I understand, the sync pin can also drive the sysref outputs if we require it?

 

Do you know the availability/status of the LMK04828 part? I have tried to source it from several suppliers but it currently has a minimum of 6 weeks lead time from some suppliers. Do you anticipate any issues with sourcing this part for the future?

 

Also, from my requirements, does it seem to be the best solution available from TI do you think?

 

Best Regards,

Fearghal

  • 0
    Intellectual 480 points

    Hi,

    If I am more specific with my question can someone assist me with my inquiry?

    As stated in my previous post, I am trying to generate 7 trigger signals using the LMK04828. I require the outputs to be synchronous to the CLKin1 input which is a clock input signal ranging from 2GHz down to 62.5MHz.

    The trigger outputs, on the SYSREF clock outputs, will be driven by either a 1 pulse per second (1PPS) signal or a user generated trigger signal. I would like to connect the 1PPS signal to the SYNC input and the generated trigger to CLKin0. From the clocking path diagram in the datasheet, I have highlighted the paths that indicate that the output trigger signals will be driven by the SYNC /CLKIN0 and synchronised with CLKIN1. Is this correct?

    In Table 5-1, the re-clocked SYNC configuration indicates that the LMK04828 will operate as I require, depending on the register settings I enable.

    Can I presume then that when I implement a delay on the SYREF clock lines, that the signals will be phase shifted in relation to the CLKIN1 signal? It seems so from section 6.3.2.5 in the datasheet. Will there be any issue with driving the sysref output clocks with the sync/clkin0 signals?

    Finally, I could not find this in the datasheet so could you tell me if there is an upper and lower frequency limit for CLKIN0 when utilised on the SYSREF clock path? Also, is there an upper/lower limit on the SYNC signal?

    Thanks,

    Fearghal

  • 0 in reply to fearghal rudden
    TI__Mastermind 28590 points

    Hello Fearghal,

    So it sounds like you are wanting to use the LMK04828 as a clock distribution with resyncing of external pulses to high speed clock?  LMK04828 can do this.  See further replies below to see if all your requirements are met.

    Do you have a volume requirement by a certain time for your project?  This device is in production so if suppliers are currently reporting lead-times, this issue will be addressed.

    fearghal rudden said:
    As stated in my previous post, I am trying to generate 7 trigger signals using the LMK04828. I require the outputs to be synchronous to the CLKin1 input which is a clock input signal ranging from 2GHz down to 62.5MHz.

    You originally mentioned 8 outputs.  Note, you can see from the above diagram you can route SYNC/SYSREF via FB_MUX via OSCout_MUX to OSCout pins.  This may allow you to eliminate the extra fan-out buffer.  I cannot comment on propagation times, so the fan-out buffer may still be the best solution for you?

    fearghal rudden said:
    The trigger outputs, on the SYSREF clock outputs, will be driven by either a 1 pulse per second (1PPS) signal or a user generated trigger signal. I would like to connect the 1PPS signal to the SYNC input and the generated trigger to CLKin0. From the clocking path diagram in the datasheet, I have highlighted the paths that indicate that the output trigger signals will be driven by the SYNC /CLKIN0 and synchronised with CLKIN1. Is this correct?

    This will work and the SYNC output would be synchronized with the CLKin1 signal on output.  However, especially on the SYNC pin, due to the high speed nature of the CLKin1, for example 2 GHz.  The edge of the high speed clock used could vary.  Setup-hold time is not defined for SYNC pin to CLKin1.  Setup-hold time for CLKin0 to CLKin1 would be improved vs. SYNC pin to CLKin1.

    fearghal rudden said:
    Will there be any issue with driving the sysref output clocks with the sync/clkin0 signals?

    No, other than the comment above about setup-and-hold times.

    fearghal rudden said:
    Finally, I could not find this in the datasheet so could you tell me if there is an upper and lower frequency limit for CLKIN0 when utilised on the SYSREF clock path? Also, is there an upper/lower limit on the SYNC signal?

    Use 40 MHz as an upper limit for SYNC pin.

    I don't have info for CLKin0 on the path you requested, I expect however should work to the 750 MHz at least.

    For low frequency SYNC pulses, 1 pps - these rates should be no issue.

    fearghal rudden said:
    • It should be possible to lock the clock to a 1pps pulse.

    We cannot lock to a 1 pps pulse, you would want to use a digital PLL for that.  However from your description, it seems like you are not locking to 1 pps pulse, but using 1 pps pulse as an input to be repeated by SYSREF output?
    fearghal rudden said:
    • It should be possible to shift each sync with 1/4 clock cycle resolution (ie 90,180,270 )

    Our digital delay only allows shifting at 1/2 clock cycle resolution.  However out analog delay is ~150 ps / step.  So up to about 1.6 GHz, you could achieve 1/4 clock cycle resolution with analog delay.  However analog delay varies more with temperature, reduces phase noise performance (should not be an issue for SYSREF), and has more non-even steps.

    73,

    Timothy

  • 0 in reply to Timothy T
    Intellectual 480 points

    Thanks Timothy,

    You're right, the 1PPS signal is an input, sorry about the confusion.

    Also, I think the fanout buffer is still our best option since we need to have a known phase relationship between the outputs on the SYSREF pins coming from the LMK04828 device.

    Thanks for answering all my questions Timothy

    Best Regards,

    Fearghal