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CDCE72010 not synchronized

Hi,

The following are the settings,

R=2 (reg.11 bit0=1); P=20 (reg.11 bit11:5 =0000111); M=N=250(F9H); Ref_in=50MHz; VCXO_in=500MHz.

I have checked Ref_in by a scope i can see it is there. The Ref_in buffer is set to AC LVDS. The VCXO input buffer is set to DC LVPECL(reg.8 bit5:0=001101). Is it right? Register 8 is set to "684000dH". it turns off the output channel 8. Register 9 is set to "6900004" it disables the channel 9.

Problem: it is not locked. Also, when checking the register 12 i got the bit4="1". Why? it actually has nothing hocked. Bit5="1", indicating the VCXO has signal.

Looking forward to your helps. Very appreciate!

Yaoting Yang