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LMK04906 worked example

Other Parts Discussed in Thread: LMK04906, CODELOADER

Good afternoon!

I use LMK04906 clock conditioner in my design. My board has 100 MHz external VCXO in PLL1 and I want to use 10 MHz reference signal at CLKin1.

I use Code Loader 4 software to configure the internal registers values. But when I load them to LMK04906 it doesn't have anything on its outputs.

I've successfully transmitted external VCXO signal to CLK4 output, so my uWire interface seems to work correctly and output buffer does work too.

It looks like internal VCO doesn't start or something. I guess, that even if it is unlocked, it should generate sine output at default frequency (or maybe floating frequency). 

Maybe something wrong with SYNC?

Does anybody can share lmk04906 worked example registers values?

I have: dual PLL, Int VCO, VCO = 2400 MHz, CLKout4 should be 2400 MHz (no divider) LVDS, CLKout0 should be 1200 MHz (div=2) LVPECL

Ref_freq = 10 MHz,

R1=10

N1 = 100

PDF1 = 1 MHz

VCXO = OSCin = 100 MHz

R2= 20 (doubler on)

PN2 =2

N2 = 120

PDF2 = 10 MHz

VCO = 2400 MHz

And registers:

R0 (INIT) 0x80160140
R0 0x00140040
R1 0x80140141
R2 0x80140142
R3 0x80140043
R4 0x00140024
R5 0x80140145
R6 0x04440006
R7 0x01010007
R8 0x04010008
R9 0x55555549
R10 0x9142410A
R11 0x0401900B
R12 0x1B0C006C
R13 0x2302826D
R14 0x0200000E
R15 0x8000800F
R16 0xC1550410
R24 0x00000058
R25 0x02C9C419
R26 0xAFA8001A
R27 0x1000029B
R28 0x0140191C
R29 0x01800F1D
R30 0x02000F1E
R31 0x001F001F

As for me - everything that should be done is done, but I've got silence on CLK0 and 4.

  • Hi Sergey,

    Could you send your CodeLoader setup file (.mac)?

    What are your PLL1 and PLL2 loop filter values?

    What is the SYNC input pin set to?

    Have you tried monitoring the PLL1 DLD and PLL2 DLD lock status signals?  If either/both PLL(s) is/are not locked as indicated by DLD status pins, can you try monitoring he N counter and R counter outputs for both PLLs to check to see if the PFD input signals are locked using an oscilloscope?

    Regards,
    Alan

  • Hi Alan,

    Sure, I've attached mac-file.

    5857.2400 clk4_0 out, clk1 in 10 M.zip

    Loop filter values are similar to EVB filter values:

    PLL1

    C1_VCXO = 0.1 uF

    C2_VCXO = 0.68 uF

    R2_VCXO = 39 k

    C3_VCXO = 100 pF

    PLL2

    C1_VCO = 47 pF

    C2_VCO = 3900 pF

    R2_VCO = 620

    Internal components are at their default values.

    PLL1 & 2 are not locked. 

    PLL1_N, PLL2_N and PLL2_R seem to be ok, but I don't see anything at PLL1_R output (reference clock generator works properly and I control input clock using oscilloscope).

    Regards,

    Sergey

  • Thanks for help, the problem was in bad soldering (short circuit at CLKin2) :(

    Regards,

    Sergey