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LMK04828 SYSREF configured outputs

fearghal rudden
Intellectual 480 points
Other Parts Discussed in Thread: LMK04828

Hi,

I have recently started working on a development board that utilises the LMK04828 device to generate trigger signals on the SYSREF outputs of the device.

As explained in previous posts (http://e2e.ti.com/support/clocks/f/48/t/271522.aspx) I wish to drive the SYSREF outputs of the device by the CLKin 0/SYNC inputs.

My design is as follows:

1856.LMK04828_Design.pdf

There are no pull-up/down resistors or AC coupling capacitors on the EXT_TRIGIN signal into the CLKin0 pin. I am driving a 10MHz signal with a Vp-p of 2.3V (VIL = 0V and VOH = 2.3V) into CLKin0. I am not driving the SYNC or CLKin1 pins with anything for now since I only want to output the signal on CLKin0. I am using the CLKSEL0 pin as an SPI readback but am not using the CLKSEL1 or STATUS_LD pins.

I have been able to configure the CLKSEL0 pin and can readback the expected device ID so my SPI interface is working.

So I believe my issue is with the settings I am currently trying to use since all I am seeing is DC voltages of 1.32V on the SYSREF output pins using my current setup. The settings I have programmed are:

Register 0x000 - (00010000) - disable 3 wire mode

Register 0x104, 0x10C, 0x114, 0x11C, 0x124, 0x12C, 0x134 - (00100000) -  sysref Output from Mux, sysref 0 (reserved) cycle digital delay, 0 half steps 

Register 0x105, 0x10D, 0x115, 0x11D, 0x125, 0x12D, 0x135 - (00010000) - sysref analog delay enabled with 0ps delay

Register 0x106, 0x10E, 0x116, 0x11E, 0x126, 0x12E, 0x136 - (11111000) - Device clock circuitry powered down, SDCLKoutY_DIS_MODE in normal operation, SDCLKoutY powered up

Register 0x107, 0x10F, 0x117, 0x11F, 0x127, 0x12F, 0x137 - (01010000) -  LVPECL 1600mV, normal polarity and DCLK power down

Register 0x138 - (01000000) - CLKin selected as dist path source, OSCout powered down

Register 0x139 - (00000011) - Sysref continuous (can be SYNC/Pulser/Re-clocked)

Register 0x140 - (11110001) - Powerdown PLL1, VCO_LDO, VCO, OSCin port and SYSREF Pulser. Everything else powered up

Register 0x143 - (00010000) - SYSREF_CLR is cleared, SYNC is enabled(bit 4), SYNC mode is disabled

Register 0x144 - (00000000) - SYNC_DISSYSREF, SYNC_DISX - all 0's prevent clocks from becoming synchronised during SYNC event.

Register 0x145 - (01111111) - Fixed Register programmed to 127

Register 0x146 - (00011001) - enable auto mode for CLKin1 and 0, CLKin configured for diff signals, CLKin0 type MOS

Register 0x147 - (00000000) - active high CLKin pol, CLKin0 manual (40 for auto mode), CLKin1 to Fin - Ext Osc, CLKin0 to Sysref Mux

Register 0x148 - (00110011) - SPI readback, push-pull pin

Then I perform a read on Register 0x003 - Read the ID_DEVICE_TYPE and I get a value of 6 which is expected.


Would you be able to help me figure out what I am doing wrong here and why I am seeing nothing on the ouput? The value of 1.32V I am reading indicates to me that the sysref outputs are switched on but are constantly low.

Thank you,

Fearghal

  • 0
    Intellectual 480 points

    Following up on this issue, I have tested the following:

    • I have read back every register I have written to confirming that there is no issue with my serial interface to the device.
    • I have configured the device to directly output the CLKin1 input clock (100MHz) to each of the SYSREF outputs.
    On review of my settings above, I failed to set the RESET register bit to 1 on power up and I had powered down the CLKoutX_Y_PD register bits. Thus I would not have seen anything on the output pin. The settings I configured (in the order shown) to output CLKin1 directly on the 7 SYSREF pins were as follows:
    Register 0x000 - (10000000) - Reset the device

    Register 0x000 - (00010000) - disable 3 wire mode

    Register 0x103, 0x10B, 0x113, 0x11B, 0x123, 0x12B, 0x133 - (00000010) -  DCLKout bypass divider, digital and analog delay to output buffer

    Register 0x104, 0x10C, 0x114, 0x11C, 0x124, 0x12C, 0x134 - (00000010) -  Device Clk Output from Mux, sysref 2 (value 1) cycle digital delay, 0 half steps

    Register 0x105, 0x10D, 0x115, 0x11D, 0x125, 0x12D, 0x135 - Leave as default

    Register 0x106, 0x10E, 0x116, 0x11E, 0x126, 0x12E, 0x136 - (11110001) - Device clock delay/step circuitry powered down, CLKoutX_Y powered up, SDCLKoutY_DIS_MODE in normal operation, SDCLKoutY powered down

    Register 0x107, 0x10F, 0x117, 0x11F, 0x127, 0x12F, 0x137 - (01010000) -  Sysref normal polarity and LVPECL 1600mV. DCLK normal polarity and power down      

    Register 0x138 - (01000000) - CLKin selected as dist path source, OSCout powered down

    Register 0x139 - (00000011) - Sysref continuous

    Register 0x140 - (11110111) - Powerdown PLL1, VCO_LDO, VCO, OSCin port, SYSREF, SYSREF_DDLY and SYSREF Pulser

    Register 0x143 - (00000000) - SYSREF_CLR is cleared, SYNC is disabled, SYNC mode is disabled

    Register 0x144 - (00000000) - SYNC_DISSYSREF, SYNC_DISX - all 0's prevent clocks from becoming synchronised during SYNC event.

    Register 0x146 - (00000001) - disable auto mode for all, CLKin1 configured for diff signals, CLKin0 type MOS

    Register 0x147 - (00000010) - active high CLKin pol, CLKin0 manual (40 for auto mode), CLKin1 to Fin - Ext Osc, CLKin0 to PLL1

    Register 0x148 - (00110011) - SPI readback, push-pull pin

    As stated in my previous post, I am looking to distribute CLKin0 input signal to the SYSREF output pins. At the moment, I do not care what settings (e.g. delay) are configured, I just wish to see the same or divided down CLKin0 signal on each of the outputs. Currently all I see is a DC output of roughly 2V on each output. The different settings I configured are highlighted below:

    Register 0x104, 0x10C, 0x114, 0x11C, 0x124, 0x12C, 0x134 - (00100010) -  SYSREF Output from Mux, sysref 2 (value 1) cycle digital delay, 0 half steps

    Register 0x106, 0x10E, 0x116, 0x11E, 0x126, 0x12E, 0x136 - (11110000) - Device clock delay/step circuitry powered down, CLKoutX_Y powered up, SDCLKoutY_DIS_MODE in normal operation, SDCLKoutY powered up

    Register 0x139 - (00000000) - Normal Sync on SYSREF outputs

    Register 0x140 - (11110001) - Powerdown PLL1, VCO_LDO, VCO, OSCin port and SYSREF Pulser

    Register 0x143 - (00010000) - SYSREF_CLR is cleared, SYNC is enabled, SYNC mode is disabled

    Register 0x147 - (00010000) - active high CLKin pol, CLKin1 manual (40 for auto mode), CLKin1 to Fin - Ext Osc, CLKin0 to Sysref Mux


    I have the following questions if you are able to help me?:

    1. Do I need to configure the ODL and IDL settings? I am driving a 10MHz signal with a Vp-p of 2.3V (VIL = 0V and VOH = 2.3V) into the CLKin0 pin. Is this correct? Or do I need a greater swing?
    2. Should the SDCLKoutY_PD be driven low for my configuration when driving the SYSREF pins from CLKin0? It does not state the register setting in the datasheet.
    3. From the diagram in figure 5-2 in the datasheet, SYNC_MODE configured to 0 should enable the CLKin0 to drive the SYSREF outputs. Is this correct?
    4. Are my configurations for SDCLKoutY_DIS_MODE, SYNC_DISSYSREF and SYNC_DISX correct?


    Thank you,

    Rgds,

    Fearghal 

  • 0 in reply to fearghal rudden
    Intellectual 480 points

    I was able to drive the SYNC input to the SYSREF outputs by configuring SDCLKoutY_MUX to SYSREF output, Normal SYNC on SYSREF outputs, leaving SYSREF functions powered up, generating SYNC from sync pin

    I eventually was able to drive the SYSREF outputs from the CLKin0 input by configuring the CLKin_SEL_MODE to CLKin0 Manual which was not clear in figure 5-2 in the datasheet.

    Rgds,

    Fearghal