Other Parts Discussed in Thread: CDCE62002, CDCE62005
I am using CDCE62002 and CDCE62005 to generate several clocks. And the clock topology is as follow:
CDCE62005 generates a 25MHz clock to the REF+/- pins of the CDCE62002, in order to test the CDCE62002 device, generate two 25MHz clocks.
When configure the CDCE62005 through spi interface, the CECE62005 can lock successfully, and the output clock is right (25MHz).
But, when configure the CECE62002 through spi interface, the lock status change constantly. The program used for CDCE62002 is almost same as for CDCE62005, so I think the reason is not the interface program.
The register value used for CDCE62002 are generated by CDCE62002 GUI software.
The configure procedure is as follow:
REG0: 32’h56e8_00e0
REG1: 32’h8382_A001
REG2: 32’h0102_1802
REG3: 32’h0002_1802
REG3: 32’h0102_1802
Also between the registers, there is a 2ms delay.
After configure, the CECE62002 does not lock, and the lock pin change between low and high.
Why?