Other Parts Discussed in Thread: ADS1672
Hello,
I need to sample two analog channels with two ADS1672 devices in bypass mode. The channels need to be sampled synchronously. Clock requirements: Fs=20MHz, single-ended, 5V High CMOS. Jitter and channel-channel skew is especially important in this design.
For better performance I plan to isolate both devices as best as I can including isolating the clocks but still keeping them synchron. The concept is to use a clock distribution IC with two synchronous differential outputs and feeding them into a step-up-converter with clipping diodes. This is covered in TI's document "slyt422" by Thomas Neu, especially in figure 26 on page 8.
Would you recommend using that concept for those particular ADCs?
Alternatively I'd use a high-speed comparator to terminate the 100 Ohms LVDS line into a 5V CMOS single-ended voltage. That way the signals are not really isolated and that way would probably be more expensive.
Which way would you recommend?
Sincerly