TI Part suggestion for System Clock level translation

Periyasamy Balasubramanian

Other Parts Discussed in Thread: LMK00105

Hi,

I"m getting System clock from the base board to clock the FPGA in my daughter card. The system clock is ~166MHz with voltage level of 1.8V or 3.3V (programmable in base board). I need to interface this SYSCLK to GCLK of FPGA port which will have VCCIO voltage of either 1.8V or 2.5V or 3.3V (programmable, supply from base board).

Please suggest a TI device to support all possible level translation combination from VDD1(1.8V/3.3V) to VDD2(1.8V/2.5V/3.3V) without delay.

Kindly check & suggest TI part ASAP.

Thank you.

over 11 years ago

0 Periyasamy Balasubramanian over 11 years ago

Prodigy 215 points

Gentle Reminder.. :-)

0 Alan O over 11 years ago

TI__Mastermind 32575 points

You may consider LMK00105, which has separate core supply voltage and 2 independent output supply voltages (2 output banks).

Regards,
Alan

0 Periyasamy Balasubramanian over 11 years ago in reply to Alan O

Prodigy 215 points

Hi Alan,

Thanks the part suggestion but the part is having core voltage 2.5V/3.3V & flexible output voltage levels (1.5/1.8/2.5/3.3V). hence i think I may not input 1.8V LVCMOS clock with 2.5V core supply. could you please suggest any other part/ yoursuggestion.

Thanks.

0 Alan O over 11 years ago in reply to Periyasamy Balasubramanian

TI__Mastermind 32575 points

LMK00105 can take a 1.8V LVCMOS input on CLKin. CLKin single-ended input voltage swing spec (Vi_se) is 0.15 Vpp (min) to 2 Vpp (max). See Figure 8 and Figure 9 for AC coupled and DC coupled single-ended input configurations, respectively.

Regards,
Alan

Clock & timing

Clock & timing forum

TI Part suggestion for System Clock level translation